Abstract: This disclosure relates generally to a method and system for latency optimized heterogeneous deployment of convolutional neural network (CNN). State-of-the-art methods for optimal deployment of convolutional neural network provide a reasonable accuracy. However, for unseen networks the same level of accuracy is not attained. The disclosed method provides an automated and unified framework for the convolutional neural network (CNN) that optimally partitions the CNN and maps these partitions to hardware accelerators yielding a latency optimized deployment configuration. The method provides an optimal partitioning of the CNN for deployment on heterogeneous hardware platforms by searching network partition and hardware pair optimized for latency while including communication cost between hardware. The method employs performance model-based optimization algorithm to optimally deploy components of a deep learning pipeline across right heterogeneous hardware for high performance.

Abstract: State of the art techniques used for document processing and particularly for handling processing of images for data extraction have the disadvantage that they have large computational load and memory footprint. The disclosure herein generally relates to text processing, and, more particularly, to a method and system for generating a data model for text extraction from documents. The system prunes a pretrained base model using a Lottery Ticket Hypothesis (LTH) algorithm, to generate a LTH pruned data model. The system further trims the LTH pruned data model to obtain a structured pruned data model, which involves discarding filters that have filter sparsity exceeding a threshold of filter sparsity. The structured pruned data model is then trained from a teacher model in a Knowledge Distillation algorithm, wherein a resultant data model obtained after training the structured pruned data model forms the data model for text detection.

Abstract: This disclosure relates generally to method and system to estimate performance of session based recommendation model layers on FPGA. Profiling is easy to perform on software based platforms such as a CPU and a GPU which have development frameworks and tool sets but on systems such as a FPGA, implementation risks are higher and important to model the performance prior to implementation. The disclosed method analyses a session based recommendation (SBR) model layers for performance estimation. Further, a network bandwidth is determined to process each layer of the SBR model based on dimensions. Performance of each layer of the SBR model is estimated at a predefined frequency by creating a layer profile comprising a throughput and a latency in one or more batches. Further, the method deploys an optimal layer on at least one of a heterogeneous hardware based on the estimated performance of each layer profile on the FPGA.

Abstract: State of the art techniques provide dedicated High-Level Synthesis (HLS) performance estimator tools that can give insights on performance bottlenecks, stall rate, stall cause etc., in HLS designs. These estimators often limit themselves to simple loop topologies and limited pragma use which makes them unreliable for large designs with complex datapaths. Embodiments herein provide a method and system for non-intrusive profiling for high-level synthesis HLS based applications. The method provides a cycle-accurate, fine-grained performance profiling framework that is non-intrusive and provides an end-to-end profile of the design. Such profiling tool can help the designer/DSE tool to quickly identify the performance bottlenecks and have a guided approach towards tuning it.

Abstract: This disclosure generally relates to high-level synthesis (HLS) platforms, and, more particularly, enable print functionality in high-level synthesis (HLS) platforms. The recent availability FPGA-HLS is a great success due to availability of compilers for FPGAs as opposed to hardware description languages (HDLs) that requires special skills. However, the compilers within the HLS design platform includes limited support for all the standard libraries, wherein features like print functionality is not supported. The invention discloses techniques to enable print functionality in HLS design platforms based on source-to-source transformations and stream combining scheme. In addition to enabling print functionality, the invention also discloses a formatter technique to receive-format FPGA data into human interpretable data.

Abstract: This disclosure generally relates to high-level synthesis (HLS) platforms, and, more particularly, enable print functionality in high-level synthesis (HLS) platforms. The recent availability FPGA-HLS is a great success due to availability of compilers for FPGAs as opposed to hardware description languages (HDLs) that requires special skills. However, the compilers within the HLS design platform includes limited support for all the standard libraries, wherein features like print functionality is not supported. The invention discloses techniques to enable print functionality in HLS design platforms based on source-to-source transformations and stream combining scheme. In addition to enabling print functionality, the invention also discloses a formatter technique to receive-format FPGA data into human interpretable data.