Abstract: A semiconductor package includes a plurality of metal leads and a semiconductor die attached to the plurality of metal leads by an interconnect. A surface of the plurality of metal leads, a metallized surface of the semiconductor die, and/or a surface of the interconnect comprises Cu and has a thermal conductivity in a range of 340 to 400 W/mK and an electrical conductivity in a range of 80 to 110% IACS. One or more of the surfaces which comprise Cu and have a thermal conductivity in the range of 340 to 400 W/mK and an electrical conductivity in the range of 80 to 110% IACS also includes micropores having a diameter in a range of 1 ?m to 10 ?m. A method of manufacturing a metal surface with such micropores also is described.

Abstract: A leadframe, that is to be incorporated into a semiconductor housing is provided. The leadframe may include a first die pad, a second die pad and a plurality of contact pads. A lower surface of the contact pads and a lower surface of the first die pad are arranged in a first plane. An upper surface of the second die pad is arranged in a second plane distant from the first plane by an overall thickness of the semiconductor package.

Abstract: A semiconductor package includes a mold compound, a plurality of electrically conductive leads at least some of which transition from a first level within the mold compound to a second (different) level outside the mold compound, and a semiconductor die embedded in the mold compound and attached to the plurality of electrically conductive leads in a flip-chip configuration. One or more leads of the plurality of electrically conductive leads includes a first section terminating at a side face of the mold compound or protruding from the side face with a first end positioned outside a footprint of the mold compound and which terminates at the second level, and a second section embedded in the mold compound and having a second end which is positioned under the semiconductor die and exposed at a bottom side of the semiconductor package. Corresponding methods of manufacture are also described.

Abstract: A semiconductor package includes a plurality of metal leads and a semiconductor die attached to the plurality of metal leads by an interconnect. A surface of the plurality of metal leads, a metallized surface of the semiconductor die, and/or a surface of the interconnect comprises Cu and has a thermal conductivity in a range of 340 to 400 W/mK and an electrical conductivity in a range of 80 to 110% IACS. One or more of the surfaces which comprise Cu and have a thermal conductivity in the range of 340 to 400 W/mK and an electrical conductivity in the range of 80 to 110% IACS also includes micropores having a diameter in a range of 1 ?m to 10 ?m. A method of manufacturing a metal surface with such micropores also is described.

Abstract: Embodiments of chip-package and corresponding methods of manufacture are provided. In an embodiment of a chip-package, the chip-package includes: a carrier having a first side and a second side opposing the first side; a first chip coupled to the first side of the carrier; a second chip coupled to the second side of the carrier; an encapsulation with a first portion, which at least partially encloses the first chip on the first side of the carrier, and a second portion, which at least partially encloses the second chip on the second side of the carrier; a via extending through the first portion of the encapsulation, the carrier and the second portion of the encapsulation; and an electrically conductive material at least partly covering a sidewall of the via in the first portion or the second portion of the encapsulation, to electrically contact the carrier at either side.

Abstract: A semiconductor package includes a frame having an insulative body with a first main surface and a second main surface opposite the first main surface, a first plurality of metal traces at the first main surface, and a first cavity in the insulative body. A thermally and/or electrically conductive material filling the first cavity in the insulative body and having a different composition than the first plurality of metal traces. The thermally and/or electrically conductive material provides a thermally and/or electrically conductive path between the first and the second main surfaces of the insulative body. A semiconductor die attached to the frame at the first main surface of the insulative body is electrically connected to the first plurality of metal traces and to the thermally and/or electrically conductive material filling the first cavity in the insulative body. A corresponding method of manufacture is also described.

Abstract: A semiconductor package includes a frame having an insulative body with a first main surface and a second main surface opposite the first main surface, a first plurality of metal traces at the first main surface, and a first cavity in the insulative body. A thermally and/or electrically conductive material filling the first cavity in the insulative body and having a different composition than the first plurality of metal traces. The thermally and/or electrically conductive material provides a thermally and/or electrically conductive path between the first and the second main surfaces of the insulative body. A semiconductor die attached to the frame at the first main surface of the insulative body is electrically connected to the first plurality of metal traces and to the thermally and/or electrically conductive material filling the first cavity in the insulative body. A corresponding method of manufacture is also described.

Abstract: Embodiments of chip-package and corresponding methods of manufacture are provided. In an embodiment of a chip-package, the chip-package includes: a carrier having a first side and a second side opposing the first side; a first chip coupled to the first side of the carrier; a second chip coupled to the second side of the carrier; an encapsulation with a first portion, which at least partially encloses the first chip on the first side of the carrier, and a second portion, which at least partially encloses the second chip on the second side of the carrier; a via extending through the first portion of the encapsulation, the carrier and the second portion of the encapsulation; and an electrically conductive material at least partly covering a sidewall of the via in the first portion or the second portion of the encapsulation, to electrically contact the carrier at either side.

Abstract: A leadframe, that is to be incorporated into a semiconductor housing is provided. The leadframe may include a first die pad, a second die pad and a plurality of contact pads. A lower surface of the contact pads and a lower surface of the first die pad are arranged in a first plane. An upper surface of the second die pad is arranged in a second plane distant from the first plane by an overall thickness of the semiconductor package.