Patents by Inventor Nurul Amin
Nurul Amin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8203875Abstract: An anti-parallel diode structure and method of fabrication is presently disclosed. In some embodiments, an anti-parallel diode structure has a semiconductor region comprising a first insulator layer disposed between a first semiconductor layer and a second semiconductor layer. The semiconductor region can be bound on a first side by a first metal material and bound on a second side by a second metal material so that current below a predetermined value is prevented from passing through the semiconductor region and current above the predetermined value passes through the semiconductor region.Type: GrantFiled: January 27, 2011Date of Patent: June 19, 2012Assignee: Seagate Technology LLCInventors: Nurul Amin, Insik Jim, Venugopalan Vaithyanathan, Wei Tian, YoungPil Kim
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Patent number: 8203870Abstract: An apparatus and associated method for a non-volatile memory cell, such as a multi-bit magnetic random access memory cell. In accordance with various embodiments, a first magnetic tunnel junction (MTJ) is adjacent to a second MTJ having a magnetic filter. The first MTJ is programmed to a first logical state with a first magnetic flux while the magnetic filter absorbs the first magnetic flux to prevent the second MTJ from being programmed.Type: GrantFiled: November 23, 2010Date of Patent: June 19, 2012Assignee: Seagate Technology LLCInventors: Nurul Amin, Dimitar V. Dimitrov, Haiwen Xi, Song S. Xue
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Publication number: 20120149183Abstract: A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.Type: ApplicationFiled: February 20, 2012Publication date: June 14, 2012Applicant: SEAGATE TECHNOLOGY LLCInventors: Young Pil Kim, Nurul Amin, Dadi Setiadi, Venugopalan Vaithyanathan, Wei Tian, Insik Jin
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Patent number: 8199570Abstract: An apparatus and associated method for a multi-bit memory capable of being selected with a magnetic layer. Various embodiments of the present invention are generally directed to a first selection layer with a low coercivity that is disposed between first and second storage layers that each have a high coercivity. In response to magnetic saturation of the first selection layer, programming of a logical state to the second storage layer is allowed.Type: GrantFiled: October 7, 2010Date of Patent: June 12, 2012Assignee: Seagate Technology LLCInventors: Nurul Amin, Johannes Van Ek
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Patent number: 8198181Abstract: A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.Type: GrantFiled: February 20, 2012Date of Patent: June 12, 2012Assignee: Seagate Technology LLCInventors: Young Pil Kim, Nurul Amin, Dadi Setiadi, Venugopalan Vaithyanathan, Wei Tian, Insik Jin
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Publication number: 20120127786Abstract: An apparatus and associated method for a non-volatile memory cell, such as a multi-bit magnetic random access memory cell. In accordance with various embodiments, a first magnetic tunnel junction (MTJ) is adjacent to a second MTJ having a magnetic filter. The first MTJ is programmed to a first logical state with a first magnetic flux while the magnetic filter absorbs the first magnetic flux to prevent the second MTJ from being programmed.Type: ApplicationFiled: November 23, 2010Publication date: May 24, 2012Applicant: SEAGATE TECHNOLOGY LLCInventors: Nurul Amin, Dimitar V. Dimitrov, Haiwen Xi, Song S. Xue
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Patent number: 8158964Abstract: A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.Type: GrantFiled: July 13, 2009Date of Patent: April 17, 2012Assignee: Seagate Technology LLCInventors: Young Pil Kim, Nurul Amin, Dadi Setiadi, Venugopalan Vaithyanathan, Wei Tian, Insik Jin
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Publication number: 20120087186Abstract: An apparatus and associated method for a multi-bit memory capable of being selected with a magnetic layer. Various embodiments of the present invention are generally directed to a first selection layer with a low coercivity that is disposed between first and second storage layers that each have a high coercivity. In response to magnetic saturation of the first selection layer, programming of a logical state to the second storage layer is allowed.Type: ApplicationFiled: October 7, 2010Publication date: April 12, 2012Applicant: SEAGATE TECHNOLOGY LLCInventors: Nurul Amin, Johannes Van Ek
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Publication number: 20120040496Abstract: Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. An electrically insulating oxide layer separates the ion conductor solid electrolyte material from the electrochemically active electrode.Type: ApplicationFiled: October 21, 2011Publication date: February 16, 2012Applicant: SEAGATE TECHNOLOGY LLCInventors: Ming Sun, Michael Xuefei Tang, Insik Jin, Venkatram Venkatasamy, Philip George Pitcher, Nurul Amin
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Publication number: 20120032131Abstract: Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. An electrically insulating oxide layer separates the ion conductor solid electrolyte material from the electrochemically active electrode.Type: ApplicationFiled: October 21, 2011Publication date: February 9, 2012Applicant: SEAGATE TECHNOLOGY LLCInventors: Ming Sun, Michael Xuefei Tang, Insik Jin, Venkatram Venkatasamy, Philip George Pitcher, Nurul Amin
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Patent number: 8098455Abstract: A magnetic device includes a write element having a write element tip and a conductive coil for carrying a current to induce a first field from the write element. A conductor proximate the write element tip carries the current to generate a second field that augments the first field. A driver provides the current to the conductive coil and the conductor, and a circuit phase shifts the current through the conductor relative to the current through the conductive coil.Type: GrantFiled: June 27, 2007Date of Patent: January 17, 2012Assignee: Seagate Technology LLCInventors: Stefan A. Ionescu, Ladislav R. Pust, Michael T. Johnson, Nurul Amin
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Patent number: 8058646Abstract: Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. An electrically insulating oxide layer separates the ion conductor solid electrolyte material from the electrochemically active electrode.Type: GrantFiled: February 23, 2009Date of Patent: November 15, 2011Assignee: Seagate Technology LLCInventors: Ming Sun, Michael Xuefei Tang, Insik Jin, Venkatram Venkatasamy, Philip George Pitcher, Nurul Amin
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Publication number: 20110228599Abstract: A non-volatile memory cell with a programmable unipolar switching element, and a method of programming the memory element are disclosed. In some embodiments, the memory cell comprises a programmable bipolar resistive sense memory element connected in series with a programmable unipolar resistive sense switching element. The memory element is programmed to a selected resistance state by application of a selected write current in a selected direction through the cell, wherein a first resistance level is programmed by passage of a write current in a first direction and wherein a second resistance level is programmed by passage of a write current in an opposing second direction. The switching element is programmed to a selected resistance level to facilitate access to the selected resistance state of the memory element.Type: ApplicationFiled: May 27, 2011Publication date: September 22, 2011Applicant: SEAGATE TECHNOLOGY LLCInventors: Wei Tian, Nurul Amin, Insik Jin, Ming Sun, Venu Vaithyanathan, YoungPil Kim, Chulmin Jung
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Patent number: 7974117Abstract: A non-volatile memory cell with a programmable unipolar switching element, and a method of programming the memory element are disclosed. In some embodiments, the memory cell comprises a programmable bipolar resistive sense memory element connected in series with a programmable unipolar resistive sense switching element. The memory element is programmed to a selected resistance state by application of a selected write current in a selected direction through the cell, wherein a first resistance level is programmed by passage of a write current in a first direction and wherein a second resistance level is programmed by passage of a write current in an opposing second direction. The switching element is programmed to a selected resistance level to facilitate access to the selected resistance state of the memory element.Type: GrantFiled: July 6, 2009Date of Patent: July 5, 2011Assignee: Seagate Technology LLCInventors: Wei Tan, Nurul Amin, Insik Jim, Ming Sun, Venu Vaithyanathan, YoungPil Kim, Chulmin Jung
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Patent number: 7965589Abstract: A device comprises a recordable disc, a substrate adjacent to the recordable disc, and an actuation mechanism fixed to the substrate. The recordable disc includes a base layer and a recordable layer on the base layer. Additional electrodes or magnetic components may be placed on the base layer to provide electromagnetic or electrostatic forces to rotate the recordable disc when acted on by the actuation mechanism. As an example, the invention may utilize MEMS techniques in order to integrate a disc and motor of a disc drive as a common component.Type: GrantFiled: January 23, 2007Date of Patent: June 21, 2011Assignee: Seagate Technology LLCInventors: Roger Hipwell, Nurul Amin, John Pendray, Andrew White, Bradley Ver Meer, Hans Leuthold, Menachem Rafaelof, Wayne Bonin
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Patent number: 7957091Abstract: A device comprises a fluid bearing including a textured fluid bearing surface and a second surface and a recordable disc. The recordable disc includes a substrate, a recordable media layer on the substrate, and at least one of the textured fluid bearing surface and the second surface. The device may be manufactured using MEMS techniques. MEMS techniques provide the high precision necessary to create the textured fluid bearing surface. MEMS techniques also allow the recordable disc to be batch-fabricated with one or more additional recordable discs.Type: GrantFiled: January 23, 2007Date of Patent: June 7, 2011Assignee: Seagate Technology LLCInventors: Roger Hipwell, Nurul Amin, John Pendray, Andrew White, Bradley Ver Meer, Hans Leuthold, Menachem Rafaelof, Wayne Bonin
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Publication number: 20110122678Abstract: An anti-parallel diode structure and method of fabrication is presently disclosed. In some embodiments, an anti-parallel diode structure has a semiconductor region comprising a first insulator layer disposed between a first semiconductor layer and a second semiconductor layer. The semiconductor region can be bound on a first side by a first metal material and bound on a second side by a second metal material so that current below a predetermined value is prevented from passing through the semiconductor region and current above the predetermined value passes through the semiconductor region.Type: ApplicationFiled: January 27, 2011Publication date: May 26, 2011Applicant: SEAGATE TECHNOLOGY LLCInventors: Nurul Amin, Insik Jin, Venugopalan Vaithyanathan, Wei Tian, YoungPil Kim
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Patent number: 7911833Abstract: An anti-parallel diode structure and method of fabrication is presently disclosed. In some embodiments, an anti-parallel diode structure has a semiconductor region comprising a first insulator layer disposed between a first semiconductor layer and a second semiconductor layer. The semiconductor region can be bound on a first side by a first metal material and bound on a second side by a second metal material so that current below a predetermined value is prevented from passing through the semiconductor region and current above the predetermined value passes through the semiconductor region.Type: GrantFiled: July 13, 2009Date of Patent: March 22, 2011Assignee: Seagate Technology LLCInventors: Nurul Amin, Insik Jin, Venugopalan Vaithyanathan, Wei Tian, YoungPil Kim
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Publication number: 20110007546Abstract: An anti-parallel diode structure and method of fabrication is presently disclosed. In some embodiments, an anti-parallel diode structure has a semiconductor region comprising a first insulator layer disposed between a first semiconductor layer and a second semiconductor layer. The semiconductor region can be bound on a first side by a first metal material and bound on a second side by a second metal material so that current below a predetermined value is prevented from passing through the semiconductor region and current above the predetermined value passes through the semiconductor region.Type: ApplicationFiled: July 13, 2009Publication date: January 13, 2011Applicant: SEAGATE TECHNOLOGY LLCInventors: Nurul Amin, Insik Jin, Venugopalan Vaithyanathan, Wei Tian, YoungPil Kim
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Publication number: 20110007545Abstract: A non-volatile memory cell and method of use thereof. In some embodiments, an individually programmable resistive sense memory (RSM) element is connected in series with a programmable metallization cell (PMC) switching element. In operation, while the switching element is programmed to a first resistive state, no current passes through the RSM element and while a second resistive state is programmed to the RSM element, current passes through the RSM element.Type: ApplicationFiled: July 13, 2009Publication date: January 13, 2011Applicant: SEAGATE TECHNOLOGY LLCInventors: Insik Jin, YoungPil Kim, Ming Sun, Chulmin Jung, Venugopalan Vaithyanathan, Nurul Amin, Wei Tian, Yong Lu