Patents by Inventor NVIDIA Corporation

NVIDIA Corporation has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140329593
    Abstract: Method and system for efficient character entry using a game controller. A computer implemented method allows a user to select any character in a subsection of a virtual input array by interacting with a single physical key on the game controller. Characters in a subsection of the virtual input array are arranged in a pattern. The number of keystrokes for selecting a particular character corresponds to the position of the particular character with reference to the pattern of the subsection.
    Type: Application
    Filed: May 6, 2013
    Publication date: November 6, 2014
    Applicant: NVIDIA Corporation
    Inventor: NVIDIA Corporation
  • Publication number: 20140328485
    Abstract: Systems and methods to deliver live sound with enhanced quality conveyed by a mixing desk to a mobile computing device user contemporaneously with external live sounds. The mobile computing device is operable to receive enhanced audio signals produced by a remote audio signal processing device through a communication work. A memory resident application is configured to playback the enhanced audio signals in phase with the external sounds using an audio rendering device. An attendee at the live event can hear the sounds from the playback through an earphone coupled to the mobile computing device as well as from the ambient environment.
    Type: Application
    Filed: May 6, 2013
    Publication date: November 6, 2014
    Applicant: NVIDIA Corporation
    Inventor: NVIDIA Corporation
  • Publication number: 20140219482
    Abstract: A flat panel electronic device and an audio playing apparatus thereof are provided. The audio playing apparatus comprises an audio generator, a plurality of speakers, a sensor and a controller. The audio generator is operable to generate a left channel audio and a right channel audio. The plurality of speakers are configured such that at least one pair of speakers is symmetrically disposed at a left side and a right side of the flat panel electronic device no matter how the flat panel electronic device is placed. The sensor is operable to detect a placed state of the flat panel electronic device in the installed state. The controller is operable to receive a detecting signal from the sensor so as to control the at least one pair of speakers to play the left channel audio and the right channel audio correspondingly according to the placed state of the flat panel electronic device.
    Type: Application
    Filed: April 17, 2013
    Publication date: August 7, 2014
    Applicant: Nvidia Corporation
    Inventor: Nvidia Corporation
  • Publication number: 20140184633
    Abstract: A method for rendering paths. The method includes accessing data comprising a path, stenciling the path, wherein a bounding region of a plurality of stencil samples updated during the stenciling is accumulated, and provoking GPU hardware to produce a rasterized region for covering the bounding region as one object without interior edges.
    Type: Application
    Filed: December 31, 2012
    Publication date: July 3, 2014
    Applicant: NVIDIA CORPORATION
    Inventor: NVIDIA Corporation
  • Publication number: 20140185951
    Abstract: Methods are provided to perform area summation of various subsections of data values in a regular input array of one or several dimensions and varying sizes. The summation is achieved by adding up values from a ripmap of partial sums, where the partial sums are computed from the input array using a binary reduction method. According to such embodiments, the generation of the ripmap of partial sums will employ several binary reduction stages. Within each stage, a reduction operator is used that adds two elements along the respective direction. This is repeated until the output is only one element wide in the respective direction. The addresses of partial sums in the ripmap may subsequently be computed using a binary analysis of the target subsections in order to choose those partial sum values for a desired area that results in the desired area sum using an optimal number of data fetches.
    Type: Application
    Filed: December 31, 2012
    Publication date: July 3, 2014
    Applicant: NVIDIA Corporation
    Inventor: NVIDIA Corporation
  • Publication number: 20140184625
    Abstract: Data transfer techniques include transferring display surface data from a memory subsystem into a stutter buffer at a first rate until the stutter buffer is substantially full. The memory interface and/or memory of the memory subsystem may then be placed into a suspend state until the stutter buffer is substantially empty. The display surface data is transferred from the stutter buffer to display logic, at a second rate even when the memory subsystem is in a suspend state. The second rate, which is typically the rendering rate of the display, is substantially slower than the rate at which data is transferred into the stutter buffer.
    Type: Application
    Filed: December 31, 2012
    Publication date: July 3, 2014
    Applicant: NVIDIA CORPORATION
    Inventor: NVIDIA Corporation
  • Publication number: 20140183951
    Abstract: A power supply system. The power system includes a power supply controller for supplying a control signal. The power system also includes a plurality of MOSFET drivers controlled by the control signal. The power system also includes a plurality of power channels. Each of the power channels includes a plurality of MOSFETs that is controlled by a corresponding MOSFET driver. The plurality of power channels is configured to generate a plurality of power signals, wherein the control signal controls delivery of the plurality of power signals through each of the power channels.
    Type: Application
    Filed: December 31, 2012
    Publication date: July 3, 2014
    Applicant: NVIDIA CORPORATION
    Inventor: NVIDIA Corporation
  • Publication number: 20140188963
    Abstract: A method for correcting a shift error in a fused multiply add operation. The method comprises adjusting a normalized floating-point number before performing a shift error correction to produce an adjusted normalized floating-point number, and correcting a shift error in the adjusted normalized floating-point number. The correcting the shift error comprises shifting a mantissa of the adjusted normalized floating-point number in one direction. A fused multiply add module comprising a normalizer module, a compensation logic, and a round. The normalizer module is operable to normalize a floating-point number to produce a normalized floating-point number. The floating-point number is normalized based upon an estimated quantity of leading zeros. The compensation logic is operable to manage a correction of a shift error in the normalized floating-point number. The rounder is operable to correct the shift error with a mantissa shift in only one direction.
    Type: Application
    Filed: December 31, 2012
    Publication date: July 3, 2014
    Applicant: NVIDIA CORPORATION
    Inventor: Nvidia Corporation
  • Publication number: 20140181540
    Abstract: A power source for supplying power to a mobile computing system comprising a Li polymer battery coupled in parallel with a supercapacitor cell battery. The Li polymer battery supplies substantially all the continuous currents demanded by the system load. The supercapacitor cell battery supplies substantially all the transient current demanded by the system load. The Li polymer battery may charge the supercapacitor cell battery when the voltage difference is larger than the difference caused by internal impedance difference.
    Type: Application
    Filed: December 26, 2012
    Publication date: June 26, 2014
    Applicant: NVIDIA CORPORATION
    Inventor: NVIDIA CORPORATION
  • Publication number: 20140177716
    Abstract: A method for using an average motion vector in a motion vector search process. The method includes accessing an input frame for processing and reading average motion vector information from memory. The method further includes performing a motion vector search by using the average motion vector and a plurality of hints, calculating a winner motion vector based on the average motion vector and the plurality of hints, and storing the winner motion vector back into memory to create a new updated average motion vector. The method further includes finishing processing the input frame using the winning motion vector.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Applicant: NVIDIA Corporation
    Inventor: NVIDIA Corporation
  • Publication number: 20140156891
    Abstract: A method for automatically generating master-slave latch structures is disclosed. A method includes, from another logic synthesis system that invokes a logic synthesis system for generating master-slave latch structures, accessing high level design descriptions of a master-slave latch structure that indicate a fully registered flow control structure design and based on the high level design descriptions, generating a master-slave latch structure design to include at least one master-slave latch pair.
    Type: Application
    Filed: December 4, 2012
    Publication date: June 5, 2014
    Applicant: NVIDIA CORPORATION
    Inventor: NVIDIA Corporation
  • Publication number: 20140132612
    Abstract: Techniques for selecting a boot display device in the multi-GPU configured computing device include a graphic initialization routine for determining a topology of a plurality of GPUs. It is then determined if a display is coupled to any of the plurality of GPUs. The determination of whether the display is coupled to a GPU is communicated to the other of the plurality of GPUs based upon the determined topology. Thereafter, selection of a given GPU as a primary boot device, by a system initialization routine, is influenced by representing each GPU not coupled to the display as a graphics device and the GPUs coupled to a given display as the primary boot device if one or more displays are coupled to GPUs, and by representing the given GPU as the primary boot device and all other GPUs as graphics devices when the display is not coupled to any of the GPUs.
    Type: Application
    Filed: April 19, 2013
    Publication date: May 15, 2014
    Applicant: NVIDIA Corporation
    Inventor: NVIDIA Corporation
  • Publication number: 20140071102
    Abstract: Dynamic white point management techniques include determining a white point of ambient light proximate to a display. A color profile adjustment is determined based upon the determined white point and intensity of the ambient light. The image color space is transformed to a display color space for rendering on the display based on the determined adjusted to the color profile.
    Type: Application
    Filed: December 31, 2012
    Publication date: March 13, 2014
    Applicant: NVIDIA CORPORATION
    Inventor: NVIDIA CORPORATION
  • Publication number: 20140043333
    Abstract: A method for compiling a shader for execution by a graphics processor. The method comprises selecting a shader for execution. A key is computed for the selected shader. A memory is searched for a copy of the computed key. A shader binary stored in the memory is passed to the graphics processor for execution if the copy of the computed key is located in the memory. Otherwise, the shader is compiled to produce the shader binary for execution by the graphics processor and storing the shader binary in the memory. The shader binary is associated with the computed key and the copy of the computed key.
    Type: Application
    Filed: December 31, 2012
    Publication date: February 13, 2014
    Applicant: NVIDIA CORPORATION
    Inventor: NVIDIA Corporation
  • Publication number: 20130221354
    Abstract: A device and method for providing access to a signal of a flip chip semiconductor die. A hole is bored into a semiconductor die to a test probe point. The hole is backfilled with a conductive material, electrically coupling the test probe point to a signal redistribution layer. A conductive bump of the signal redistribution layer is electrically coupled to a conductive contact of a package substrate. An external access point of the package substrate is electrically coupled to the conductive contact, such that signals of the flip chip semiconductor die are accessible for measurement at the external access point.
    Type: Application
    Filed: January 22, 2013
    Publication date: August 29, 2013
    Applicant: NVIDIA CORPORATION
    Inventor: NVIDIA Corporation
  • Publication number: 20130216013
    Abstract: A system and method are provided for determining a time for safely sampling a signal of a dock domain. In one embodiment, a frequency estimate of a first clock domain is calculated utilizing a frequency estimator. Additionally, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the frequency estimate. In another embodiment, a frequency estimate of a first dock domain is calculated utilizing a frequency estimator. Further, a phase estimate of the first clock domain is calculated based on the frequency estimate, utilizing a phase estimator. Moreover, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the phase estimate.
    Type: Application
    Filed: March 22, 2013
    Publication date: August 22, 2013
    Applicant: NVIDIA CORPORATION
    Inventor: NVIDIA CORPORATION
  • Publication number: 20130214839
    Abstract: One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a single-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The single-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. The output signal Q is set or reset at the rising clock edge using a single-trigger sub-circuit. A set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.
    Type: Application
    Filed: March 28, 2013
    Publication date: August 22, 2013
    Applicant: NVIDIA Corporation
    Inventor: NVIDIA Corporation
  • Publication number: 20130212417
    Abstract: A central processing unit (CPU) can specify an initial (e.g., baseline) frequency for a clock signal used by a device to perform a task. The CPU is then placed in a reduced power mode. The device performs the task after the CPU is placed in the reduced power mode until a triggering event causes the device to send an interrupt to the CPU. In response to the interrupt, the CPU awakens to dynamically adjust the clock frequency. If the clock frequency is reset to the baseline value, then the CPU is again placed in the reduced power mode.
    Type: Application
    Filed: February 4, 2013
    Publication date: August 15, 2013
    Applicant: NVIDIA CORPORATION
    Inventor: NVIDIA CORPORATION
  • Publication number: 20130176251
    Abstract: A touch-screen input/output device including a touch sensor, a display, a display control module, a touch sensor control module and a synchronizer module. The touch sensor is overlaid on a display. The display control module is communicatively coupled to the display and converts video data into a serial bit stream video display signal include one or more blanking intervals. The touch sensor control module is communicatively coupled to the touch sensor and determines touch events and location of the touch event on the touch sensor during one or more touch sensor scan cycles. The synchronizer module is communicatively coupled between the display control module and the touch sensor control module, and interleaves the one or more touch sensor scan cycles with the one or more blanking intervals of the video display signal.
    Type: Application
    Filed: December 31, 2012
    Publication date: July 11, 2013
    Applicant: NVIDIA CORPORATION
    Inventor: NVIDIA CORPORATION
  • Publication number: 20130179711
    Abstract: A method for graphics processor clock scaling comprises the following steps. A percentage of idle-time is calculated, based upon an elapsed idle-time and an elapsed active time. A graphics processor clock rate is reduced if the percentage of idle time is higher than a high limit threshold. The graphics processor clock rate is increased if the percentage of idle time is lower than a low limit threshold.
    Type: Application
    Filed: December 12, 2012
    Publication date: July 11, 2013
    Applicant: NVIDIA CORPORATION
    Inventor: NVIDIA Corporation