Patents by Inventor Nyles Wynn Cody

Nyles Wynn Cody has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10811498
    Abstract: A method for making a semiconductor device may include forming a superlattice on a substrate comprising a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Moreover, forming at least one of the base semiconductor portions may include overgrowing the at least one base semiconductor portion and etching back the overgrown at least one base semiconductor portion.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: October 20, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson
  • Patent number: 10777451
    Abstract: A semiconductor device may include a semiconductor substrate having a trench therein, and a superlattice liner at least partially covering bottom and sidewall portions of the trench. The superlattice liner may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a semiconductor cap layer on the superlattice liner and having a dopant constrained therein by the superlattice liner, and a conductive body within the trench.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: September 15, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Robert John Stephenson, Richard Burton, Dmitri Choutov, Nyles Wynn Cody, Daniel Connelly, Robert J Mears, Erwin Trautmann
  • Patent number: 10727049
    Abstract: A method for making a semiconductor device may include forming a recess in a substrate including a first Group IV semiconductor, forming an active layer comprising a Group III-V semiconductor within the recess, and forming a buffer layer between the substrate and active layer and comprising a second Group IV semiconductor. The method may further include forming an impurity and point defect blocking superlattice layer adjacent the buffer layer.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: July 28, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson
  • Publication number: 20200135489
    Abstract: A method for making a semiconductor device may include forming a superlattice layer and an adjacent semiconductor layer. The superlattice layer may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include diffusing nitrogen into the superlattice layer.
    Type: Application
    Filed: October 31, 2018
    Publication date: April 30, 2020
    Inventors: KEITH DORAN WEEKS, NYLES WYNN CODY, MAREK HYTHA, ROBERT J. MEARS, ROBERT JOHN STEPHENSON, LOUIS NICHOLAS HUTTER, III
  • Publication number: 20200075731
    Abstract: A method for making a semiconductor device may include forming a superlattice on a substrate comprising a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Moreover, forming at least one of the base semiconductor portions may include overgrowing the at least one base semiconductor portion and etching back the overgrown at least one base semiconductor portion.
    Type: Application
    Filed: August 30, 2018
    Publication date: March 5, 2020
    Inventors: KEITH DORAN WEEKS, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson
  • Publication number: 20200075327
    Abstract: A semiconductor device may include a substrate and a superlattice on the substrate including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Furthermore, an upper portion of at least one of the base semiconductor portions adjacent the respective at least one non-semiconductor monolayer may have a defect density less than or equal to 1×105/cm2.
    Type: Application
    Filed: August 30, 2018
    Publication date: March 5, 2020
    Inventors: Keith Doran WEEKS, Nyles Wynn CODY, Marek HYTHA, Robert J. MEARS, Robert John STEPHENSON
  • Patent number: 10566191
    Abstract: A semiconductor device may include a substrate and a superlattice on the substrate including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Furthermore, an upper portion of at least one of the base semiconductor portions adjacent the respective at least one non-semiconductor monolayer may have a defect density less than or equal to 1×105/cm2.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: February 18, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson
  • Patent number: 10468245
    Abstract: A semiconductor device may include a substrate including a first Group IV semiconductor having a recess therein, an active layer comprising a Group III-V semiconductor within the recess, and a buffer layer between the substrate and active layer and comprising a second Group IV semiconductor. The semiconductor device may further include an impurity and point defect blocking superlattice layer adjacent the buffer layer.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: November 5, 2019
    Assignee: ATOMERA INCORPORATED
    Inventors: Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson
  • Publication number: 20190279868
    Abstract: A semiconductor device may include a substrate including a first Group IV semiconductor having a recess therein, an active layer comprising a Group III-V semiconductor within the recess, and a buffer layer between the substrate and active layer and comprising a second Group IV semiconductor. The semiconductor device may further include an impurity and point defect blocking superlattice layer adjacent the buffer layer.
    Type: Application
    Filed: March 9, 2018
    Publication date: September 12, 2019
    Inventors: Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson
  • Publication number: 20190279897
    Abstract: A method for making a semiconductor device may include forming a trench in a semiconductor substrate, and forming a superlattice liner covering bottom and sidewall portions of the trench. The superlattice liner may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a semiconductor cap layer on the superlattice liner and having a dopant constrained therein by the superlattice liner, and forming a conductive body within the trench.
    Type: Application
    Filed: March 8, 2019
    Publication date: September 12, 2019
    Inventors: Robert John Stephenson, Richard Burton, Dmitri Choutov, Nyles Wynn Cody, Daniel Connelly, Robert J. Mears, Erwin Trautmann
  • Publication number: 20190280090
    Abstract: A semiconductor device may include a semiconductor substrate having a trench therein, and a superlattice liner at least partially covering bottom and sidewall portions of the trench. The superlattice liner may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a semiconductor cap layer on the superlattice liner and having a dopant constrained therein by the superlattice liner, and a conductive body within the trench.
    Type: Application
    Filed: March 8, 2019
    Publication date: September 12, 2019
    Inventors: ROBERT JOHN STEPHENSON, RICHARD BURTON, DMITRI CHOUTOV, NYLES WYNN CODY, DANIEL CONNELLY, ROBERT J, MEARS, ERWIN TRAUTMANN
  • Publication number: 20190279869
    Abstract: A method for making a semiconductor device may include forming a recess in a substrate including a first Group IV semiconductor, forming an active layer comprising a Group III-V semiconductor within the recess, and forming a buffer layer between the substrate and active layer and comprising a second Group IV semiconductor. The method may further include forming an impurity and point defect blocking superlattice layer adjacent the buffer layer.
    Type: Application
    Filed: March 9, 2018
    Publication date: September 12, 2019
    Inventors: KEITH DORAN WEEKS, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson
  • Patent number: 10109479
    Abstract: A method for making a semiconductor device may include forming a superlattice on a semiconductor substrate including a respective plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Further, at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween. The method may further include epitaxially forming a semiconductor layer on the superlattice, and annealing the superlattice to form a buried insulating layer in which the at least some semiconductor atoms are no longer chemically bound together through the at least one non-semiconductor monolayer therebetween.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: October 23, 2018
    Assignee: ATOMERA INCORPORATED
    Inventors: Robert J. Mears, Robert John Stephenson, Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha
  • Patent number: 6429103
    Abstract: A method of fabricating an Emode HIGFET semiconductor device, and the device, is disclosed including epitaxially growing by metal-organic chemical vapor deposition an epitaxial buffer. The buffer includes a layer of short-lifetime gallium arsenide on a gallium arsenide substrate and a layer of aluminum gallium arsenide on the layer of short-lifetime gallium arsenide. The short-lifetime gallium arsenide is grown at a temperature below approximately 550° C. so as to have a lifetime less than approximately 500 picoseconds. A stack of compound semiconductor layers is then epitaxially grown on the layer of aluminum gallium arsenide of the buffer and an Emode field effect transistor is formed in the stack.
    Type: Grant
    Filed: April 13, 2000
    Date of Patent: August 6, 2002
    Assignee: Motorola, Inc.
    Inventors: Eric Shanks Johnson, Nyles Wynn Cody