Abstract: The present invention provides a clock-shared differential signaling interface and a method of driving output data to a display panel. The apparatus includes a plurality of driver circuits, wherein each driver circuit in the plurality of driver circuits respectively provides output data. The apparatus also includes a timing controller providing a first clock signal to the plurality of driver circuits via a multi-drop connection, and providing a respective differential data signal to each driver circuit via a respective point-to-point connection.

Abstract: The phase detection circuit may allow an operating speed of a semiconductor circuit to be increased irrespective of whether a combinational logic circuit within the semiconductor circuit operates at lower operating speeds. The phase detection circuit may adjust a data rate of an input data signal and selectively enable reference signals and error signals. The phase detection circuit may be included within a clock data recovery circuit.

Abstract: The present invention provides a clock-shared differential signaling interface and a method of driving output data to a display panel. The apparatus includes a plurality of driver circuits, wherein each driver circuit in the plurality of driver circuits respectively provides output data. The apparatus also includes a timing controller providing a first clock signal to the plurality of driver circuits via a multi-drop connection, and providing a respective differential data signal to each driver circuit via a respective point-to-point connection.

Abstract: A circuit for recovering a clock signal may include a frequency multiplier configured to generate a plurality of local clock signals, each having a different phase, based on a plurality of received global clock signals at a first frequency and each having a different phase. The local clock signals may be generated at a second frequency higher than the first frequency. The circuit may include a phase interpolator configured to generate a recovered clock signal at a given phase and at a third frequency, based on the generated local clock signals, and a phase shifter configured to adjust the phase of the recovered clock signal so as to synchronize the phase of the recovered clock signal with a phrase of input data that is input to the phase shifter.

Abstract: A quarter-rate clock recovery circuit includes a clock generator, a phase interpolation unit, a phase detector, and a controller. The clock generator generates first through fourth clocks having a quarter frequency of a data-rate of input data, the second, third and fourth clocks have phase differences of 90, 180, and 270 degrees with respect to a phase of the first clock, respectively. The phase interpolation unit performs a phase interpolation on the first through fourth clocks based on control signals to generate fifth through eighth clocks that have a quarter frequency of the data-rate of the input data, the fifth clock tracking a phase of the input data, the sixth, seventh, and eighth clocks respectively have phase differences of 45, 90, and 135 degree with respect to a phase of the fifth clock. The phase detector outputs signals corresponding to phase differences between the input data and the fifth through eighth clocks based on the input data and the fifth through eighth clocks.

Abstract: A level shifter and method thereof. The level shifter may include a protective circuit configured to receive an input signal having an input voltage level, the input signal received on an input line, the protective circuit reducing the input voltage level to generate a stabilized input signal and a first inverter configured to invert the stabilized input signal and to output an inverted output signal at an inverted output voltage level to a first node. In an example method, an input signal may be received at an input voltage level, the input voltage level may be reduced to output a stabilized input signal, the stabilized input signal may be inverted to output an inverted output signal at an inverted output voltage level to a first node and the first node may be transitioned to a node voltage level based on the input signal. The level shifter and method thereof may reduce a power consumption and/or a chip size of a semiconductor device.

Abstract: A recovery circuit may include a phase detector, a quadrant decision unit, a quadrant controller, a charge pump unit, and a phase interpolator. The phase detector may compare a phase of input data with a phase of a current output clock to generate first up signal and first down signal and the quadrant decision unit may determine the phase location for the current output clock and output quadrant decision signals based on a phase location. The quadrant controller may output a second up signal and a second down signal based on the first up signal and the first down signal and the quadrant decision signals, and the charge pump unit may output a first and second phase control voltage based on the second up signal and the second down signal. The phase interpolator may select clocks from a plurality of clocks based on the quadrant decision signals and output an output clock signal based on the selected clocks.

Abstract: A variable voltage gain amplifier in an automatic voltage gain control circuit includes a denominator current source that generates a denominator current corresponding to a denominator a numerator current source that generates a numerator current corresponding to a numerator, and a differential amplifier that amplifies an input voltage with a variable voltage gain and generates an output voltage that is substantially dB-linear with the input voltage when the variable voltage gain that is expressed as an exponential function of a control voltage is approximated to a fraction where each of a denominator and a numerator is expressed as a third order polynomial function of the control voltage.

Abstract: First and fourth phase difference signals, and first and second phase difference information signals respectively having first, fourth, second and third phase differences may be generated using an input signal and a plurality of clock signals each of which has different phase with each other. A level of the first phase difference information signal may be lowered, and a second phase difference signal having a first level less than levels of the first and fourth phase difference signals may be generated. A level of the second phase difference information signal may be lowered, and a third phase difference signal having a second level less than the levels of the first and fourth phase difference signals may be generated. The level of the phase difference signals having a phase difference lower than 45° may be lowered, and thus the operational speed of a CDR device may be maintained and/or the jitter characteristics may be enhanced.

Abstract: A quarter-rate clock recovery circuit includes a clock generator, a phase interpolation unit, a phase detector, and a controller. The clock generator generates first through fourth clocks having a quarter frequency of a data-rate of input data, the second, third and fourth clocks have phase differences of 90, 180, and 270 degrees with respect to a phase of the first clock, respectively. The phase interpolation unit performs a phase interpolation on the first through fourth clocks based on control signals to generate fifth through eighth clocks that have a quarter frequency of the data-rate of the input data, the fifth clock tracking a phase of the input data, the sixth, seventh, and eighth clocks respectively have phase differences of 45, 90, and 135 degree with respect to a phase of the fifth clock. The phase detector outputs signals corresponding to phase differences between the input data and the fifth through eighth clocks based on the input data and the fifth through eighth clocks.

Abstract: The phase detection circuit may allow an operating speed of a semiconductor circuit to be increased irrespective of whether a combinational logic circuit within the semiconductor circuit operates at lower operating speeds. The phase detection circuit may adjust a data rate of an input data signal and selectively enable reference signals and error signals. The phase detection circuit may be included within a clock data recovery circuit.

Abstract: A level shifter and method thereof. The level shifter may include a protective circuit configured to receive an input signal having an input voltage level, the input signal received on an input line, the protective circuit reducing the input voltage level to generate a stabilized input signal and a first inverter configured to invert the stabilized input signal and to output an inverted output signal at an inverted output voltage level to a first node. In an example method, an input signal may be received at an input voltage level, the input voltage level may be reduced to output a stabilized input signal, the stabilized input signal may be inverted to output an inverted output signal at an inverted output voltage level to a first node and the first node may be transitioned to a node voltage level based on the input signal. The level shifter and method thereof may reduce a power consumption and/or a chip size of a semiconductor device.

Abstract: A circuit for recovering a clock signal may include a frequency multiplier configured to generate a plurality of local clock signals, each having a different phase, based on a plurality of received global clock signals at a first frequency and each having a different phase. The local clock signals may be generated at a second frequency higher than the first frequency. The circuit may include a phase interpolator configured to generate a recovered clock signal at a given phase and at a third frequency, based on the generated local clock signals, and a phase shifter configured to adjust the phase of the recovered clock signal so as to synchronize the phase of the recovered clock signal with a phrase of input data that is input to the phase shifter.

Abstract: First and fourth phase difference signals, and first and second phase difference information signals respectively having first, fourth, second and third phase differences may be generated using an input signal and a plurality of clock signals each of which has different phase with each other. A level of the first phase difference information signal may be lowered, and a second phase difference signal having a first level less than levels of the first and fourth phase difference signals may be generated. A level of the second phase difference information signal may be lowered, and a third phase difference signal having a second level less than the levels of the first and fourth phase difference signals may be generated. The level of the phase difference signals having a phase difference lower than 45° may be lowered, and thus the operational speed of a CDR device may be maintained and/or the jitter characteristics may be enhanced.