Abstract: Each of the signal processing units of a digital signal processing system is provided with a programmable timing delay unit having identical programming interface to control the signal timing of its signal processing circuitry. Additionally, a central timing unit is provided to the digital signal processing system to provide signal timing control inputs to the programmable timing delay units. Furthermore, a routing switcher is provided to the digital signal processing system to control configuration of the signal path, i.e. the order in which the signal is processed by all or a subset of the signal processing units of the digital signal processing system. As a result, the individual signal processing units are relieved the burden of providing circuitry for timing control, delay equalization and timing derivation.

Abstract: A computer editing system graphical user interface includes at least one central processing unit (CPU) coupled through appropriate input/output (I/O) circuitry to input devices, such as a cursor control device, and a display device. The CPU is further coupled to a storage device for the storage of data and programs including a database. The database comprises a plurality of source logs indicating a beginning point and an ending point defining all the available source material for the corresponding source log. An output sequence of selected source material is displayed on a timeline as source material blocks, wherein the source material blocks are defined by a head point and a tail point. Through the computer editing system, a user performs a variety of re-editing functions to trim existing source material and to insert new source material on the timeline. When performing a re-edit function, all available source material blocks for a source log selected for re-edit is displayed.

Abstract: A flexible computer controlled non-linear transform generator is disclosed which employs a random access memory (RAM) lookup table (LUT) having programmable controlled address and data paths and an address multiplexer which is programmed to dynamically control LUT loading and live data transformation. A MASK register is programmed to dynamically modify the number of banks of memory in the LUT, an ADDRESS SELECT register is programmed to set the access mode of for the LUT--either random access mode, auto-increment mode, or live data mode, a BIT WIDTH register is programmed to set the width of the data stored in the LUT, and a BASE ADDRESS register is programmed with the starting address for loading the LUT in auto-increment mode. During live data transformation, a digitized input signal is used to address the LUT, while the contents of the LUT at the addressed location provides a digitized output signal according to a predefined transfer function.

Abstract: A hardware implementation of a digitized image corrector is disclosed that converts a colorimetric representation of an original image into a new representation based upon the colors of the original and target images, as well as user supplied artistic parameters. The digitized image corrector receives digitized Red, Green and Blue input signals that comprise a colorimetric representation of an original film scene, and generates digitized Red, Green, and Blue output signals according to the specifications of SMPTE 240 M. The digitized image corrector is comprised of four identical hardware correction modules, which are coupled to receive correction parameters from an external source. Each module has a bypass switch for entering a bypass mode, which is used for reconfiguration of the module's correction parameters without affecting the output image.