Abstract: A method for generating or refining an OPC model for use in wafer fabrication. A predetermined feature layout is used to prepare a mask for use in, for example, a photolithographic process. The mask is used to create structures corresponding to mask features on a semiconductor wafer using the mask. Measurements of the actual mask features and wafer features may then be assessed and correlated, and the results used to generate an OPC model or refine an existing one. In addition, the OPC may be used to simulate a fabrication operation by applying the OPC tool to a predetermined layout to produce a mask image and a wafer image, and then comparing the predetermined layout to the simulated wafer image to determine at least one fitness value.

Abstract: A design for a crack stop and moisture barrier for a semiconductor device includes a plurality of discrete conductive features formed at the edge of an integrated circuit proximate a scribe line. The discrete conductive features may comprise a plurality of staggered lines, a plurality of horseshoe-shaped lines, or a combination of both.

Abstract: A method of preventing resist line collapse in damascene structures and a structure thereof is disclosed. A damascene pattern for resist lines is enhanced with ribs extending therefrom. The ribs provide mechanical support for resist lines and improve the lithography process for forming the resist lines, particularly when a negative focus is used. The ribs may extend between vias in an underlying material layer. The method results in structurally strong resist lines for damascene structures that are less likely to collapse.