Abstract: Methods and systems for controlling scheduling in a packet switching node in a network are provided which enable the scheduling of packets from different sources in an earliest deadline first order. The packets are assigned timestamp deadlines and placed in input queues. The timestamps are determined according to maximum delay or minimum throughput quality of service requirements specified for the packets. The packets are scheduled in the earliest deadline first order in an output packet store. The packet closest to its timestamp deadline is selected from the output packet store by using an index.

Abstract: Methods and systems for controlling scheduling in a packet switching node in a network are provided which enable the scheduling of packets from different sources in an earliest deadline first order. The packets are assigned timestamp deadlines and placed in input queues. The timestamps are determined according to maximum delay or minimum throughput quality of service requirements specified for the packets. The packets are scheduled in the earliest deadline first order in an output packet store. The packet closest to its timestamp deadline is selected from the output packet store by using an index.

Abstract: A method and apparatus for detecting errors in a data packet being transmitted as a set of smaller data cells by performing operations on the Cyclic Redundancy Check (CRC) values of the individual cells. An error detection apparatus initializes a memory area with a first value. The apparatus generates a CRC value for a first data cell. The apparatus combines the first value and the CRC value for the first cell in a XOR operation and the apparatus stores the result in a memory location. For subsequent cells in the data packet, the apparatus generates a cell CRC value, shifts the value in the memory location twelve times, and replaces the shifted value in the memory location with a new value generated from a XOR operation performed on the shifted value and the cell CRC value. The apparatus compares the final value in the memory location with an end comparison value and generates an error signal if the final and comparison values are different.