Abstract: Provided are power device packages, which include thermal electric modules using the Peltier effect and thus can improve operational reliability by rapidly dissipating heat generated during operation to the outside, and methods of fabricating the same. An exemplary power device package includes: a thermal electric module having a first surface and a second surface opposite each other, and a plurality of n-type impurity elements and a plurality of p-type impurity elements alternately and electrically connected to each other in series; a lead frame attached to the first surface of the thermal electric module by an adhesive member; at least one power semiconductor chip and at least one control semiconductor chip, each chip being mounted on and electrically connected to the lead frame; and a sealing member sealing the thermal electric module, the chips, and at least a portion of the lead frame, but exposing the second surface of the module.

Abstract: Provided are power device packages, which include thermal electric modules using the Peltier effect and thus can improve operational reliability by rapidly dissipating heat generated during operation to the outside, and methods of fabricating the same. An exemplary power device package includes: a thermal electric module having a first surface and a second surface opposite each other, and a plurality of n-type impurity elements and a plurality of p-type impurity elements alternately and electrically connected to each other in series; a lead frame attached to the first surface of the thermal electric module by an adhesive member; at least one power semiconductor chip and at least one control semiconductor chip, each chip being mounted on and electrically connected to the lead frame; and a sealing member sealing the thermal electric module, the chips, and at least a portion of the lead frame, but exposing the second surface of the module.

Abstract: Provided is a power device package including: a substrate including at least one first die attach region; at least one first power semiconductor chip and at least one second power semiconductor chip that are stacked in order on the first die attach region; at least one die attach paddle that is disposed between the at least one first power semiconductor chip and the at least one second power semiconductor chip, wherein the die attach paddle comprises an adhesive layer that is attached to a top surface of the first power semiconductor chip; a conductive pattern including a second die attach region, on which the second semiconductor chip is mounted, and a wire bonding region that is electrically connected to the second die attach region; and an interlayer member between the adhesive layer and the conductive pattern; and a plurality of firs leads electrically connected to at least one of the at least one first power semiconductor chip and the at least one second power semiconductor chip.

Abstract: Provided is a power device package including: a substrate including at least one first die attach region; at least one first power semiconductor chip and at least one second power semiconductor chip that are stacked in order on the first die attach region; at least one die attach paddle that is disposed between the at least one first power semiconductor chip and the at least one second power semiconductor chip, wherein the die attach paddle comprises an adhesive layer that is attached to a top surface of the first power semiconductor chip; a conductive pattern including a second die attach region, on which the second semiconductor chip is mounted, and a wire bonding region that is electrically connected to the second die attach region; and an interlayer member between the adhesive layer and the conductive pattern; and a plurality of firs leads electrically connected to at least one of the at least one first power semiconductor chip and the at least one second power semiconductor chip.

Abstract: Provided are semiconductor packages and methods of fabricating the same. An exemplary semiconductor package includes a die pad including a dimple filled with an insulating material in an upper surface or a lower surface thereof. A semiconductor chip is mounted on the upper surface of the first die pad. A package body encapsulates the first die pad and the first semiconductor chip and includes a pinhole. A bottom surface of the pinhole terminates at the insulating material.

Abstract: Provided are power device substrates that comprise thermally conductive plastic materials, and power device packages including the same. An exemplary power device package includes a power device substrate that comprises a thermally conductive plastic material, and has a first principal plane that provides an electrically insulating surface and a second principal plane of which at least a portion is exposed outside a molding member. The exemplary power device package further includes one or more power devices disposed on the first principal plane of the power device substrate, and a plurality of conductive members that are electrically connected to the power device(s) in order to electrically connect the power device(s) to an external circuit.

Abstract: Provided are power device packages, which include thermal electric modules using the Peltier effect and thus can improve operational reliability by rapidly dissipating heat generated during operation to the outside, and methods of fabricating the same. An exemplary power device package includes: a thermal electric module having a first surface and a second surface opposite each other, and a plurality of n-type impurity elements and a plurality of p-type impurity elements alternately and electrically connected to each other in series; a lead frame attached to the first surface of the thermal electric module by an adhesive member; at least one power semiconductor chip and at least one control semiconductor chip, each chip being mounted on and electrically connected to the lead frame; and a sealing member sealing the thermal electric module, the chips, and at least a portion of the lead frame, but exposing the second surface of the module.

Abstract: Provided is a power device package including: a substrate including at least one first die attach region; at least one first power semiconductor chip and at least one second power semiconductor chip that are stacked in order on the first die attach region; at least one die attach paddle that is disposed between the at least one first power semiconductor chip and the at least one second power semiconductor chip, wherein the die attach paddle comprises an adhesive layer that is attached to a top surface of the first power semiconductor chip; a conductive pattern including a second die attach region, on which the second semiconductor chip is mounted, and a wire bonding region that is electrically connected to the second die attach region; and an interlayer member between the adhesive layer and the conductive pattern; and a plurality of firs leads electrically connected to at least one of the at least one first power semiconductor chip and the at least one second power semiconductor chip.

Abstract: Provided are semiconductor packages and methods of fabricating the same. An exemplary semiconductor package includes a die pad including a dimple filled with an insulating material in an upper surface or a lower surface thereof. A semiconductor chip is mounted on the upper surface of the first die pad. A package body encapsulates the first die pad and the first semiconductor chip and includes a pinhole. A bottom surface of the pinhole terminates at the insulating material.