Abstract: A display device according to an exemplary embodiment of the present inventive concept includes: a first insulation substrate; a thin film transistor; a pixel electrode; a second insulation substrate; and a common electrode. The pixel electrode includes a first subpixel electrode including a first horizontal stem portion and a first vertical stem portion perpendicular thereto at one end of the first horizontal stem portion and a second subpixel electrode including a second vertical stem portion and a second horizontal stem portion perpendicular thereto at one end of the second horizontal stem portion, a plurality of regions in which arrangements of liquid crystal molecules are respectively different are divided by the first horizontal stem portion, the first vertical stem portion, the second horizontal stem portion, and the second vertical stem portion, and each of the plurality of regions has a longest vertical length of less than about 100 ?m.

Abstract: A curved display device according to an exemplary embodiment of the present system and method includes: a first insulation substrate; a gate line and a data line disposed on the first insulation substrate to cross each other; a thin film transistor coupled to the gate line and the data line; a pixel electrode disposed on the thin film transistor; a common electrode facing the pixel electrode; and a liquid crystal layer disposed between the pixel electrode and the common electrode and having liquid crystal molecules. The pixel electrode includes: a cross-shaped stem portion; minute branch portions extending from the cross-shaped stem portion; and minute slits disposed between the minute branch portions, wherein a width of the minute slit is greater than that of the minute branch portion.

Abstract: A display device according to an exemplary embodiment includes: a first insulation substrate; a thin film transistor disposed on the first insulation substrate; and a pixel electrode coupled to the thin film transistor. The pixel electrode includes a first subpixel electrode that is divided into two regions configured to arrange liquid crystal molecules while including one first horizontal stem portion, and a second subpixel electrode that includes a plurality of second horizontal stem portions.

Abstract: A curved liquid crystal display according to an exemplary embodiment of the present system and method includes: a first substrate; a first thin film display layer disposed at an upper surface of the first substrate; a second substrate; a second thin film display layer disposed at a lower surface of the second substrate; a sealant disposed at an edge of the first substrate and the second substrate; and a liquid crystal layer disposed between the first substrate and the second substrate and sealed by the sealant, wherein the first thin film display layer and the second thin film display layer face each other, the first substrate and the second substrate are curved to have the same degree of curvature, and a thickness of a side surface of the second substrate is thinner than a thickness of a center portion of the second substrate.

Abstract: A liquid crystal display panel is provided. The liquid crystal display panel includes a first substrate comprising a pixel area and a non-pixel area surrounding the pixel area, a thin-film transistor (TFT) disposed on the pixel area of the first substrate and a pixel electrode connected to the TFT, and a plurality of metal wirings disposed on the non-pixel area of the first substrate and one or more dummy patterns disposed adjacent to the metal wirings. The TFT includes a gate electrode, a source electrode, and a drain electrode, and the dummy patterns are formed of a same material as at least one of the gate source, the source electrode, and the drain electrode.

Abstract: Provided are a display device and a manufacturing method thereof capable of preventing aggregation of an alignment layer and maintaining uniformly a cell-gap. The display device according to an exemplary embodiment of the invention includes: a substrate including a plurality of pixel areas; a thin film transistor formed on the substrate; a pixel electrode connected to the thin film transistor and formed in the pixel area; a barrier layer formed on the pixel electrode; a roof layer formed on the barrier layer to be spaced apart from the barrier layer with a microcavity therebetween; and a liquid crystal formed to fill the microcavity.

Abstract: A thin film transistor array panel includes a first substrate, a gate line disposed on the first substrate and includes a lower layer including titanium, a middle layer including a transparent conductive material, and an upper layer including copper, a pixel electrode disposed on the first substrate and includes a lower layer including titanium, and an upper layer including the transparent conductive material, a gate insulating layer disposed on the gate line and the pixel electrode, a semiconductor layer disposed on the gate insulating layer, a data line and a drain electrode disposed on the semiconductor layer, a passivation layer which covers the data line and the drain electrode, and a common electrode disposed on the passivation layer.

Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.

Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.

Abstract: A thin-film transistor (TFT) and a method of manufacturing the same are disclosed herein. The TFT may include a gate electrode disposed on an insulating substrate, an insulating layer disposed on the insulating substrate and the gate electrode, an active layer pattern disposed on the insulating layer to overlap the gate electrode, a source electrode disposed on the insulating layer and at least part of which overlaps the active layer pattern, and a drain electrode which is separated from the source electrode and at least part of which overlaps the active layer pattern. A first ohmic contact layer pattern may be disposed between the active layer pattern and the source electrode and between the active layer pattern and the drain electrode. The first ohmic contact layer may have higher nitrogen content on its surface than in other portions of the first ohmic contact layer.

Abstract: A light emitting diode (LED), includes: a substrate; a first electrode connection line disposed on the substrate; a second electrode connection line disposed on the substrate; a first contact metal layer disposed on the first electrode connection line; a second contact metal layer disposed on the second electrode connection line; a light emitting unit disposed on the first contact metal layer and the second contact metal layer; a partition disposed on the substrate and about the light emitting unit; and an encapsulation layer covering the light emitting unit. The encapsulation layer includes a light conversion material.

Abstract: RC delay in gate lines of a wide display is reduced by using a low resistivity conductor in the gate lines and a different conductor for forming corresponding gate electrodes. More specifically, a corresponding display substrate includes a gate line made of a first gate line metal, a data line made of a first data line metal, a pixel transistor and a first connection providing part. The pixel transistor includes a first active pattern formed of polycrystalline silicon (poly-Si) and a first gate electrode formed there above and made of a conductive material different from the first gate line metal. The first connection providing part connects the first gate electrode to the gate line. On the other hand, the source electrode is integrally extended from the data line.

Abstract: Provided are a display device and a manufacturing method thereof capable of preventing aggregation of an alignment layer and maintaining uniformly a cell-gap. The display device according to an exemplary embodiment of the invention includes: a substrate including a plurality of pixel areas; a thin film transistor formed on the substrate; a pixel electrode connected to the thin film transistor and formed in the pixel area; a barrier layer formed on the pixel electrode; a roof layer formed on the barrier layer to be spaced apart from the barrier layer with a microcavity therebetween; and a liquid crystal formed to fill the microcavity.

Abstract: A thin film transistor array panel according to an exemplary embodiment of the present invention comprises a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, and a data line formed on the semiconductor layer, wherein the data line comprises a lower data layer, an upper data layer, a data oxide layer, and a buffer layer, wherein the upper data layer and the buffer layer comprise a same material.

Abstract: A method of manufacturing a thin film transistor array substrate includes forming a gate pattern on a substrate, forming a gate insulating film on the substrate, forming a source/drain pattern and a semiconductor pattern on the substrate, forming first, second, and third passivation films successively on the substrate. Over the above multi-layered passivation film forming a first photoresist pattern including a first portion formed on part of the drain electrode and on the pixel region, and a second portion. The second portion is thicker than the first portion. Then, patterning the third passivation film using the first photoresist pattern, forming a second photoresist pattern by removing the first portion of the first photoresist pattern, forming a transparent electrode film on the substrate, removing the second photoresist pattern and the transparent electrode film disposed on the second photoresist pattern, and forming a transparent electrode pattern on the second passivation layer.

Abstract: A method of manufacturing a thin film transistor array substrate includes forming a gate pattern on a substrate, forming a gate insulating film on the substrate, forming a source/drain pattern and a semiconductor pattern on the substrate, forming first, second, and third passivation films successively on the substrate. Over the above multi-layered passivation film forming a first photoresist pattern including a first portion formed on part of the drain electrode and on the pixel region, and a second portion. The second portion is thicker than the first portion. Then, patterning the third passivation film using the first photoresist pattern, forming a second photoresist pattern by removing the first portion of the first photoresist pattern, forming a transparent electrode film on the substrate, removing the second photoresist pattern and the transparent electrode film disposed on the second photoresist pattern, and forming a transparent electrode pattern on the second passivation layer.

Abstract: A method for manufacturing a thin film transistor array panel, including: sequentially forming a first silicon layer, a second silicon layer, a lower metal layer, and an upper metal layer on a gate insulating layer and a gate line; forming a first film pattern on the upper metal layer; forming a first lower metal pattern and a first upper metal pattern that includes a protrusion, by etching the upper metal layer and the lower metal layer; forming first and second silicon patterns by etching the first and second silicon layers; forming a second film pattern by ashing the first film pattern; forming a second upper metal pattern by etching the first upper metal pattern; forming a data line and a thin film transistor by etching the first lower metal pattern and the first and second silicon patterns; and forming a passivation layer and a pixel electrode on the resultant.

Abstract: RC delay in gate lines of a wide display is reduced by using a low resistivity conductor in the gate lines and a different conductor for forming corresponding gate electrodes. More specifically, a corresponding display substrate includes a gate line made of a first gate line metal, a data line made of a first data line metal, a pixel transistor and a first connection providing part. The pixel transistor includes a first active pattern formed of polycrystalline silicon (poly-Si) and a first gate electrode formed there above and made of a conductive material different from the first gate line metal. The first connection providing part connects the first gate electrode to the gate line. On the other hand, the source electrode is integrally extended from the data line.

Abstract: A method of manufacturing a thin film transistor capable of simplifying a substrate structure and a manufacturing process is disclosed. The method of manufacturing a thin film transistor array substrate comprising a three mask process. The 3 mask process comprising, forming a gate pattern on a substrate, forming a gate insulating film on the substrate, forming a source/drain pattern and a semiconductor pattern on the substrate, forming a first, second, and third passivation film successively on the substrate.

Abstract: A thin film transistor array panel according to an exemplary embodiment of the present invention comprises a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, and a data line formed on the semiconductor layer, wherein the data line comprises a lower data layer, an upper data layer, a data oxide layer, and a buffer layer, wherein the upper data layer and the buffer layer comprise a same material.