Abstract: A secondary storage facility having a drive and a controller employing multiple error recovery techniques; the controller signals the drive to try such techniques in sequence, according to descending a priori probability of success. The controller does not know or need to know the details of the error recovery procedures.

Abstract: In a system including a plurality of mass storage devices at least one of which includes first and second ports, a plurality of controllers and cables coupling the ports to various ones of the controllers and in which each device can only be on-line through one port at a time, state information is sent from the on-line port of each device to a first controller to which it is coupled until a predetermined command from the controller to the on-line port is sent by the first controller. The device responds to the predetermined command by discontinuing the sending of state information from the on-line port to the first controller, and sending a state available signal from the other port to the second controller while maintaining the actual state of said device unchanged, permitting the other controller to interrogate the device as an aid in determining system topology.

Abstract: In a data processing system including a host computer and a secondary storage system that includes a controller and a mass storage device, the device stores information regarding the physical and logical characteristics of a disk drive associated with the device. In response to a command from the controller, the device produces a signal or signals which provide information to the controller regarding the physical and logical characteristics of the disk drive. The physical and logical characteristics include the drive bit transfer rate and subunit characteristics.

Abstract: A radial bus for use in a secondary storage subsystem, between a mass storage drive and controller. The bus has four unidirectional bit-serial channels, two for carrying signals from drive to controllers. One channel carries real-time drive state information to the controller; another carries real-time controller state information to the drive. The state information is a sequence of multiplexed bits sent in continuous repetition. Most status variables are represented as a single bit in a specific place in the sequence; the set of status variables defining drive state or controller state, as the case may be, is thus provided by a sequence of bits. When such a bit changes state, a potential change of status has occurred; the change is required to persist some number of repetition of the sequence before the state change is recognized, to avoid spuriously signalling a state change.

Abstract: A self-clocking encoding technique for synchronous transmission of digital signals, and apparatus therefor. In an exemplary embodiment, the encoding technique utilizes relatively positive and negative pulses of fixed, predetermined duration. For electrical pulses, the point of reference is preferably a zero baseline. At the leading edge LE.sub.i of the i.sup.th bit cell, the value of the i.sup.th bit is encoded as a positive pulse (e.g., 82A) in the case of a logical "1" or a negative pulse (e.g., 82B) in the case of a logical "0". Further, the next subsequent (i.e., (i+l).sup.th bit has the same value, a pulse (e.g., 82D) of the opposite polarity is injected into the i.sup.th bit cell after the leading edge pulse. Thus, positive and negative pulses alternate and the information content of the encoded signal has no d.c. component; this facilitates a.c. coupling. Further, the encoding technique is bit-rate (i.e., frequency-) independent and usable over a wide range of bit transfer rates.