Abstract: An apparatus includes a comparator. The comparator includes first and second pregain stages, and a switch network coupled to the first and second pregain stages. A plurality of switches in the switch network are operable to provide a feedback path around at least one of the first and second pregain stages. The comparator further includes a latch coupled to the second pregain stage.

Abstract: An apparatus includes a comparator. The comparator includes a plurality of pregain stages, and a switch network coupled to the plurality of pregain stages. The comparator further includes a latch coupled to the plurality of pregain stages.

Abstract: An apparatus includes a comparator. The comparator includes a plurality of pregain stages, and a switch network coupled to the plurality of pregain stages. The comparator further includes a latch coupled to the plurality of pregain stages.

Abstract: An apparatus includes a comparator. The comparator includes first and second pregain stages, and a switch network coupled to the first and second pregain stages. A plurality of switches in the switch network are operable to provide a feedback path around at least one of the first and second pregain stages. The comparator further includes a latch coupled to the second pregain stage.

Abstract: A method for calibrating a successive-approximation analog-to-digital converter (ADC) includes configuring the successive-approximation ADC in a calibration mode of operation. The method includes, while in the calibration mode of operation: determining a digital code corresponding to a programmable capacitance of the successive-approximation analog-to-digital converter, and storing the digital code corresponding to the programmable capacitance in a storage element of an integrated circuit die including the successive-approximation ADC. The programmable capacitance may be a gain tuning capacitance, a bridge tuning capacitance, an offset capacitance, or a monotonicity tuning capacitance.

Abstract: A successive-approximation ADC includes an input capacitance coupled to a first node and configured to store a sampled input charge based on an input analog signal during a first phase of an analog-to-digital conversion. A gain tuning capacitance configured to store a first portion of the sampled input charge during a second phase of the analog-to-digital conversion. A charge-redistribution DAC includes a conversion capacitance configured to store a second portion of the sampled input charge during the second phase and configured to use the second portion, a remaining portion of the sampled input charge, and a reference voltage to provide an analog signal on the first node corresponding to a digital output code approximating the input analog signal at an end of the third phase. The gain tuning capacitance sequesters the first portion of the sampled input charge from the charge-redistribution DAC during the third phase.

Abstract: A method for operating an ADC includes storing a sampled input charge on a capacitance of a sample-and-hold circuit including a DAC. The sampled input charge is stored using a first reference signal coupled to the DAC and a second signal. The sampled input charge has a value based on a first digital code. The method includes converting a second digital code to an analog signal on the first node using the DAC, the sampled input charge, and the first reference signal. The second digital code is one least-significant bit different from the first digital code. The method includes generating a monotonicity indicator indicating whether an output analog signal of the DAC is monotonic in response to a transition of a digital input of the DAC from the first digital code to the second digital code based on a comparison of the analog signal to the second signal.

Abstract: In one aspect, an apparatus includes: a first time-to-data converter (TDC) to oversample a first duration of incoming data and hold the oversampled first duration during receipt of a second duration of the incoming data; a second TDC to oversample the second duration of the incoming data and hold the oversampled second duration during receipt of a third duration of the incoming data; a processing circuit coupled to the first and second TDCs, the processing circuit including a first filter to filter the oversampled first duration and the oversampled second duration and generate a control output therefrom; and a digitally controlled oscillator (DCO) coupled to the processing circuit to receive the control output and generate a recovery clock signal therefrom.

Abstract: In one aspect, an apparatus includes: a first time-to-data converter (TDC) to oversample a first duration of incoming data and hold the oversampled first duration during receipt of a second duration of the incoming data; a second TDC to oversample the second duration of the incoming data and hold the oversampled second duration during receipt of a third duration of the incoming data; a processing circuit coupled to the first and second TDCs, the processing circuit including a first filter to filter the oversampled first duration and the oversampled second duration and generate a control output therefrom; and a digitally controlled oscillator (DCO) coupled to the processing circuit to receive the control output and generate a recovery clock signal therefrom.

Abstract: In one aspect, an apparatus includes: a first time-to-data converter (TDC) to oversample a first duration of incoming data and hold the oversampled first duration during receipt of a second duration of the incoming data; a second TDC to oversample the second duration of the incoming data and hold the oversampled second duration during receipt of a third duration of the incoming data; a processing circuit coupled to the first and second TDCs, the processing circuit including a first filter to filter the oversampled first duration and the oversampled second duration and generate a control output therefrom; and a digitally controlled oscillator (DCO) coupled to the processing circuit to receive the control output and generate a recovery clock signal therefrom.

Abstract: In one aspect, a method includes: determining a power mode of a device; setting a first reference voltage level and a second reference voltage level based at least in part on the power mode; and using at least one of the first reference voltage level and the second reference voltage level for comparison against incoming data.

Abstract: In one aspect, a method includes: determining a power mode of a device; setting a first reference voltage level and a second reference voltage level based at least in part on the power mode; and using at least one of the first reference voltage level and the second reference voltage level for comparison against incoming data.

Abstract: VCONN pull-down circuits and related methods are disclosed for USB Type-C connections. A device is connected through a USB Type-C connection to a separate device using connections including a CC (configuration channel) pin and a VCONN (connection power) pin. The device pulls down the VCONN pin to ground through a resistance (Ra) by applying the voltage on the CC pin to close a switch coupled between the VCONN pin and ground. The device can also be operated in a dead-battery mode where no supply voltage is present for the device. The device can also stop the pull-down on the VCONN pin after a connection is established, for example, using additional switches coupled to a pull-down control signal to remove the CC voltage and open the switch. The voltage on the CC pin can also be clamped to a desired voltage or voltage range using a voltage clamp.

Abstract: In one aspect, a method includes: determining a power mode of a device; setting a first reference voltage level and a second reference voltage level based at least in part on the power mode; and using at least one of the first reference voltage level and the second reference voltage level for comparison against incoming data.

Abstract: In one aspect, an apparatus includes: a first time-to-data converter (TDC) to oversample a first duration of incoming data and hold the oversampled first duration during receipt of a second duration of the incoming data; a second TDC to oversample the second duration of the incoming data and hold the oversampled second duration during receipt of a third duration of the incoming data; a processing circuit coupled to the first and second TDCs, the processing circuit including a first filter to filter the oversampled first duration and the oversampled second duration and generate a control output therefrom; and a digitally controlled oscillator (DCO) coupled to the processing circuit to receive the control output and generate a recovery clock signal therefrom.

Abstract: In one aspect, an apparatus includes: a first time-to-data converter (TDC) to oversample a first duration of incoming data and hold the oversampled first duration during receipt of a second duration of the incoming data; a second TDC to oversample the second duration of the incoming data and hold the oversampled second duration during receipt of a third duration of the incoming data; a processing circuit coupled to the first and second TDCs, the processing circuit including a first filter to filter the oversampled first duration and the oversampled second duration and generate a control output therefrom; and a digitally controlled oscillator (DCO) coupled to the processing circuit to receive the control output and generate a recovery clock signal therefrom.

Abstract: In one aspect, an apparatus includes: a first time-to-data converter (TDC) to oversample a first duration of incoming data and hold the oversampled first duration during receipt of a second duration of the incoming data; a second TDC to oversample the second duration of the incoming data and hold the oversampled second duration during receipt of a third duration of the incoming data; a processing circuit coupled to the first and second TDCs, the processing circuit including a first filter to filter the oversampled first duration and the oversampled second duration and generate a control output therefrom; and a digitally controlled oscillator (DCO) coupled to the processing circuit to receive the control output and generate a recovery clock signal therefrom.

Abstract: In one aspect, a method includes: determining a power mode of a device; setting a first reference voltage level and a second reference voltage level based at least in part on the power mode; and using at least one of the first reference voltage level and the second reference voltage level for comparison against incoming data.

Abstract: VCONN pull-down circuits and related methods are disclosed for USB Type-C connections. A device is connected through a USB Type-C connection to a separate device using connections including a CC (configuration channel) pin and a VCONN (connection power) pin. The device pulls down the VCONN pin to ground through a resistance (Ra) by applying the voltage on the CC pin to close a switch coupled between the VCONN pin and ground. The device can also be operated in a dead-battery mode where no supply voltage is present for the device. The device can also stop the pull-down on the VCONN pin after a connection is established, for example, using additional switches coupled to a pull-down control signal to remove the CC voltage and open the switch. The voltage on the CC pin can also be clamped to a desired voltage or voltage range using a voltage clamp.

Abstract: In an example embodiment, an apparatus includes: a first sampling capacitor and a comparator to compare a sum voltage at a first input terminal to a voltage level at a second input terminal according to a thermometer cycle. The sum voltage is based at least in part on an analog input voltage and a divided reference voltage, where the analog input voltage and the reference voltage (VREF) are of a first voltage range and the divided reference voltage is according to ( ( 2 M - 1 ) ? V REF / 2 M ) , to enable the comparator to operate at a second voltage range, the second voltage range less than V REF / 2 M , and M is a number of bits of a digital output to be decided in the thermometer cycle and is greater than one.