Abstract: Systems or methods of the present disclosure may provide for interrupt clustering using a processor and/or system on a chip. An interrupt controller includes an input terminal configured to receive an interrupt request and an output terminal configured to output an interrupt based on the interrupt request. The interrupt controller also includes detection circuitry configured to detect that an interrupt request of the plurality of interrupt requests has been received and to start a counter for a timing group based on receiving the interrupt request. The interrupt controller also includes holding circuitry configured to hold release of an interrupt of the plurality of interrupts corresponding to the interrupt request until the counter reaches a threshold value.

Abstract: Systems or methods of the present disclosure may provide for interrupt clustering using a processor and/or system on a chip. An interrupt controller includes an input terminal configured to receive an interrupt request and an output terminal configured to output an interrupt based on the interrupt request. The interrupt controller also includes detection circuitry configured to detect whether a threshold number of interrupt requests have been received by the interrupt controller for a membership group. The interrupt controller also includes holding circuitry configured to hold release of the interrupt until the threshold number of interrupt requests has been received by the interrupt controller.

Abstract: Systems or methods of the present disclosure may provide for interrupt clustering using a processor and/or system on a chip. An interrupt controller includes an input terminal configured to receive an interrupt request and an output terminal configured to output an interrupt based on the interrupt request. The interrupt controller also includes detection circuitry configured to detect whether a threshold number of interrupt requests have been received by the interrupt controller for an external event group. The interrupt controller also includes holding circuitry configured to hold release of the interrupt and to release the held interrupts after the external event has been received by the interrupt controller.

Abstract: A single coder/decoder shared among several multiprocessors in a digital signal processing system through time-division multiplexing between multiple processors to enhance signal processing capabilities by assigning different digital-to-analog channels to different processors for digital-to-analog conversion, while allowing all processors to operate on the same analog-to-digital data for analog-to-digital conversion, thereby resulting in chip area reduction and power consumption saving.

Abstract: Large, complex SoCs comprise interconnections of various functional blocks. Such functional blocks contain scan chains that are used for their individual production testing. The present invention utilizes these scan chains as a tool in the debugging of these SoCs by providing the internal contents of registers and memories contained on the SoC device. Accordingly, both hardware and software designers are provided a means to observe the effect of their designs on the internal operation of the SoC device. The invention is compatible with current integrated circuit design methodology and requires minimal area on the SoC for support circuitry.

Abstract: Large, complex SoCs comprise interconnections of various functional blocks, which blocks frequently running on different clock domains. By effectively controlling the clocks within the SoC, this invention provides a means to halt execution of a SoC and to then single or n-cycle step its execution in a real system environment. Accordingly, the invention provides an effective debugging tool to both the SoC designer and software designers whose code is executed by the SoC as it provides them the capability of studying the cause and effect of interactions between functional blocks. The invention is also applicable to SoCs containing only one functional block while containing complex circuitry operating on a clock different than the block's clock. In particular, the invention permits halting of the block clock and then single or n-cycle stepping its execution to permit analysis of the interactions between the block and the SoC circuitry.

Abstract: The present invention provides an architecture for a peripheral device to activate a breakpoint in a processor or other device under emulation. A peripheral breakpoint active signaler allows the peripheral to signal the occurrence of a breakpoint to the processor using a halt or trap line to the processor. This invention provides developers with increased code development capabilities by allowing them to set breakpoints in a peripheral device for the benefit of a processor interfaced with the peripheral to detect when a certain external event has occurred based on the perspective of a peripheral. A breakpoint control register individually enables breakpointing capability of each peripheral with respect to having the capability to halt the processor. Each peripheral has the capability to output a breakpoint request signal to set a bit in a breakpoint status register for readback by the processor, through an external port such as a JTAG test port, or other device.

Abstract: The present invention provides a shared I/O port and a configurable interconnect allowing any of a plurality of cores to access any pin of a shared I/O port. Preferably, one of the plurality of cores is designated as a master core at least with respect to the configuration of the shared I/O port(s), and the remaining cores desiring to gain access to the shared I/O port(s) are designated as non-master or slave cores. It is the responsibility of the master core to reassign chip resources such as the shared I/O port(s) for use by either the master core or by any of the shared cores. Preferably, all shared I/O ports are controlled by default by the master core. The slave cores communicate with the master core through a suitable internal messaging system. If a slave core requires use of a particular I/O pin or I/O port not already configured appropriately for its use, the slave core will send an appropriate message to the master core through the messaging system, e.g., a dual port memory mailbox.

Abstract: A multifunction reset circuit including low power bandgap, a comparator, and an open drain buffer circuit--with the inclusion of four external components (three resistors and one capacitor) to provide undervoltage monitoring, power failure indicating, manual resetting and other reset control conditions to a single integrated circuit terminal, together with hysteresis tolerance.