Abstract: A timing controller includes a first stage removing a first surge signal generated during a first logic level period of a data enable signal, and a second stage receiving the data enable signal generated by the first stage and removing a second surge signal generated during a second logic level period of the received data enable signal.

Abstract: A timing controller provides a cable plug status detection function by receiving a reference lock signal from a graphics system connected via a constituent cable and comparing the reference lock signal to one or more reference time periods to determine the cable plug status.

Abstract: Provided are a skew adjustment circuit and a method thereof. The skew adjustment circuit inputs an input clock signal and an input start pulse signal to output an output clock signal and an output start pulse signal which are delayed according to a skew value of a skew control signal. The skew adjustment circuit includes a delay circuit, a selection circuit, and an output circuit. The delay circuit delays an input clock signal by a skew value in response to a skew control signal to generate an output clock signal. The selection circuit compares the skew control signal and an offset control signal to select one of the input start pulse signal and a delayed start pulse signal to output the selected signal as a start pulse signal. The output circuit responds to the output clock signal to output the start pulse signal as an output start pulse signal.

Abstract: A timing controller provides a cable plug status detection function by receiving a reference lock signal from a graphics system connected via a constituent cable and comparing the reference lock signal to one or more reference time periods to determine the cable plug status.

Abstract: A domino logic circuit includes an input circuit and an output circuit. The input circuit precharges a dynamic node at a first phase of a clock signal. The input circuit determines a logic level of the dynamic node by performing a logic evaluation of input data at a second phase of the clock signal. The output circuit is coupled between an output node and the dynamic node. The output circuit determines a logic level of the output node in response to the clock signal and the logic level of the dynamic node. The output circuit maintains the logic level of the output node while the logic evaluation is performed.

Abstract: A timing controller includes a first stage removing a first surge signal generated during a first logic level period of a data enable signal, and a second stage receiving the data enable signal generated by the first stage and removing a second surge signal generated during a second logic level period of the received data enable signal.

Abstract: A domino logic circuit includes an input circuit and an output circuit. The input circuit precharges a dynamic node at a first phase of a clock signal. The input circuit determines a logic level of the dynamic node by performing a logic evaluation of input data at a second phase of the clock signal. The output circuit is coupled between an output node and the dynamic node. The output circuit determines a logic level of the output node in response to the clock signal and the logic level of the dynamic node. The output circuit maintains the logic level of the output node while the logic evaluation is performed.

Abstract: Provided are a skew adjustment circuit and a method thereof. The skew adjustment circuit inputs an input clock signal and an input start pulse signal to output an output clock signal and an output start pulse signal which are delayed according to a skew value of a skew control signal. The skew adjustment circuit includes a delay circuit, a selection circuit, and an output circuit. The delay circuit delays an input clock signal by a skew value in response to a skew control signal to generate an output clock signal. The selection circuit compares the skew control signal and an offset control signal to select one of the input start pulse signal and a delayed start pulse signal to output the selected signal as a start pulse signal. The output circuit responds to the output clock signal to output the start pulse signal as an output start pulse signal.