Abstract: A multi-chip package is provided that has at least a first, second and third chip, each comprising a top and bottom surface. The multi-chip package also has a package substrate for interfacing with a printed circuit board (PCB). The chips and the package substrate are housed within an encapsulation material. The bottom surface of the first chip is attached to the package substrate. The top surface of the first chip has a first plurality of landing pads, which serve as a mechanical and electrical interface between the first and second chip. The bottom surface of the second chip has a second plurality of landing pads that serve as a mechanical and electrical interface between the second and first chip. Additionally, the top surface of the second chip has a third plurality of landing pads that serve as a mechanical and electrical interface between the second and third chip.

Abstract: A refresh scheduler is configured to refresh memory cells of a memory device according to a plurality of refresh intervals. The various refresh intervals are determined in response to refresh errors.

Abstract: Embodiments of the present invention generally provide techniques and apparatus for altering the functionality of a multi-chip package (MCP) without requiring entire replacement of the MCP. The MCP may be designed with a top package substrate designed to interface with an add-on package that, when sensed by the MCP, alters the functionality of the MCP.

Abstract: Embodiments of the invention generally provide a system, method and memory device for accessing memory. One embodiment includes synchronization circuitry configured to determine timing skew between a first memory device and a second memory device, and introduce a delta delay to at least one of the first memory device and the second memory device to adjust the timing skew.

Abstract: Embodiments of the invention generally provide a system, method, and memory device for accessing memory. In one embodiment, a first memory device includes command decoding logic configured to decode commands issued to the first memory device and a second memory device, while command decoding logic of the second memory device is bypassed.

Abstract: The present invention is generally related to integrated circuit devices, and more particularly, to methods and systems of a multi-chip package (MCP) containing a self-diagnostic scheme for detecting errors in the MCP. The MCP generally comprises a controller, at least one volatile memory chip having error detection logic, at least one non-volatile memory chip, and at least one fail signature register for storing fail signature data related to memory errors detected in the MCP. The controller can poll the fail signature register for fail signature data related to memory errors stored therein. Upon detection of fail signature data, the controller can store the fail signature data on a fail signature register located on a non-volatile memory.

Abstract: Embodiments of the invention generally provide an apparatus and technique for sharing an internally generated voltage between devices of a multi-chip package (MCP). The internally generated voltage may be shared via a conductive structure that electrically couples the devices and carries the internally generated voltage.

Abstract: A multi-chip package is provided that has at least a first, second and third chip, each comprising a top and bottom surface. The multi-chip package also has a package substrate for interfacing with a printed circuit board (PCB). The chips and the package substrate are housed within an encapsulation material. The bottom surface of the first chip is attached to the package substrate. The top surface of the first chip has a first plurality of landing pads, which serve as a mechanical and electrical interface between the first and second chip. The bottom surface of the second chip has a second plurality of landing pads that serve as a mechanical and electrical interface between the second and first chip. Additionally, the top surface of the second chip has a third plurality of landing pads that serve as a mechanical and electrical interface between the second and third chip.

Abstract: A memory includes a first macro chip, a spine chip, and a common substrate. The common substrate is configured to pass signals between the first macro chip and the spine chip. The first macro chip, the spine chip, and the common substrate provide a memory.

Abstract: The present invention is generally related to integrated circuit devices, and more particularly, to methods and systems of a multi-chip package (MCP) containing a self-diagnostic scheme for detecting errors in the MCP. The MCP generally comprises a controller, at least one volatile memory chip having error detection logic, at least one non-volatile memory chip, and at least one fail signature register for storing fail signature data related to memory errors detected in the MCP. The controller can poll the fail signature register for fail signature data related to memory errors stored therein. Upon detection of fail signature data, the controller can store the fail signature data on a fail signature register located on a non-volatile memory.

Abstract: Embodiments of the invention generally provide a system, method, and memory device for accessing memory. In one embodiment, a first memory device includes command decoding logic configured to decode commands issued to the first memory device and a second memory device, while command decoding logic of the second memory device is bypassed.

Abstract: Embodiments of the invention generally provide a system, method and memory device for accessing memory. One embodiment includes synchronization circuitry configured to determine timing skew between a first memory device and a second memory device, and introduce a delta delay to at least one of the first memory device and the second memory device to adjust the timing skew.

Abstract: Embodiments of the invention generally provide an apparatus and technique for sharing an internally generated voltage between devices of a multi-chip package (MCP). The internally generated voltage may be shared via a conductive structure that electrically couples the devices and carries the internally generated voltage.

Abstract: Embodiments of the present invention generally provide techniques and apparatus for altering the functionality of a multi-chip package (MCP) without requiring entire replacement of the MCP. The MCP may be designed with a top package substrate designed to interface with an add-on package that, when sensed by the MCP, alters the functionality of the MCP.

Abstract: A refresh scheduler is configured to refresh memory cells of a memory device according to a plurality of refresh intervals. The various refresh intervals are determined in response to refresh errors.

Abstract: A memory includes a first macro chip, a spine chip, and a common substrate. The common substrate is configured to pass signals between the first macro chip and the spine chip. The first macro chip, the spine chip, and the common substrate provide a memory.

Abstract: In a system having multiple analog circuits that share a common power supply, where a change in the operational state of one circuit can have an effect on the performance of another circuit, a determination is made when any one of the circuits enters a state where its performance could be affected. Under such a condition, the other circuits that share the common power supply are placed in a state where their effect on the operation of the first circuit will be negligible. This state for the other circuits can be one of maximum current draw, so that subsequent operation by the other circuits will not alter the demands on the power supply.

Abstract: In a system having multiple analog circuits that share a common power supply, where a change in the operational state of one circuit can have an effect on the performance of another circuit, a determination is made when any one of the circuits enters a state where its performance could be affected. Under such a condition, the other circuits that share the common power supply are placed in a state where their effect on the operation of the first circuit will be negligible. This state for the other circuits can be one of maximum current draw, so that subsequent operation by the other circuits will not alter the demands on the power supply.

Abstract: Techniques are described for analog-to-digital signal conversion. According to exemplary embodiments, a first request is associated with a changeable set of a plurality of input terminals, a second request is associated with a changeable one of the input terminals, and a third request is associated with a fixed one of the input terminals. One of the first, second, and third requests is received, and an analog signal presented at one of the input terminals is converted into a digital value based on the received one of the first, second, and third requests. When one of the second and third requests is received while converting a plurality of analog signals presented at the changeable set of the input terminals, a determination can be made whether the changeable set of the input terminals includes the one of the changeable and fixed input terminals associated with the received request.

Abstract: Techniques are described for analog-to-digital signal conversion. According to exemplary embodiments, a first request is associated with a plurality of input terminals and a second request is associated with one of the input terminals. An analog signal presented at each of a portion of the input terminals associated with the first request is converted in succession into a digital value until the one of the input terminals associated with the second request is reached. A predetermined amount of time is waited to receive the second request. An analog signal presented at each of a remaining portion of the input terminals associated with the first request is converted in succession into a digital value when one of an expiration of the predetermined amount of time and a receiving of the second request occurs.