Abstract: A biosensor system and method of its use for detecting particles on the surface of an integrated circuit is disclosed. The system can include a light source and a plurality of optical sensors formed on an integrate circuit. The particles can be positioned the surface of the integrated circuit whereby the particles can cast a shadow or shadows that reduces the amount of light transmitted from the light source to the optical sensors. The surface of the integrated circuit can include one or more optical sensing areas whereby the presence of one or more particles may significantly or measurably reduce the amount of light incident on one or more optical sensor.

Abstract: An assay system and method for use in the field of chemical testing is disclosed. The assay system can be used for filtering whole blood for testing on an integrated circuit containing digital control functionality.

Abstract: A device and method for filtering blood is disclosed herein. The device can filter blood and attach analytes within the blood to magnetic particles. The analytes can then be strongly bound to an analyzing device by a magnetic force. The analytes can then be counted by the analyzing device and the result can be displayed.

Abstract: A device and method for filtering blood is disclosed herein. The device can filter blood and attach analytes within the blood to magnetic particles. The analytes can then be strongly bound to an analyzing device by a magnetic force. The analytes can then be counted by the analyzing device and the result can be displayed.

Abstract: A device and method for filtering blood is disclosed herein. The device can filter blood and attach analytes within the blood to magnetic particles. The analytes can then be strongly bound to an analyzing device by a magnetic force. The analytes can then be counted by the analyzing device and the result can be displayed.

Abstract: A device and method for filtering blood is disclosed herein. The device can filter blood and attach analytes within the blood to magnetic particles. The analytes can then be strongly bound to an analyzing device by a magnetic force. The analytes can then be counted by the analyzing device and the result can be displayed.

Abstract: An integrated magnetic field generation and detection platform is described that is capable of manipulating and detecting individual magnetic particles, such as spherical super-paramagnetic beads, and providing biosensing functionality. The platform is implemented in an integrated circuit, a portion of the surface of which is functionalized with one or more biochemical agents that binds tightly (i.e., specifically) with a target analyte. The magnetic beads are similarly functionalized with one or more biochemical agents that that bind specifically with the target analyte. When a sample is introduced, magnetic beads that specifically bind to the integrated circuit can be separated from non-specifically bound beads and detected.

Abstract: A biosensor system and method of its use for detecting particles on the surface of an integrated circuit is disclosed. The system can include a light source and a plurality of optical sensors formed on an integrate circuit. The particles can be positioned the surface of the integrated circuit whereby the particles can cast a shadow or shadows that reduces the amount of light transmitted from the light source to the optical sensors. The surface of the integrated circuit can include one or more optical sensing areas whereby the presence of one or more particles may significantly or measurably reduce the amount of light incident on one or more optical sensor.

Abstract: A device and method for filtering blood is disclosed herein. The device can filter blood and attach analytes within the blood to magnetic particles. The analytes can then be strongly bound to an analyzing device by a magnetic force. The analytes can then be counted by the analyzing device and the result can be displayed.

Abstract: An integrated magnetic field generation and detection platform is described that is capable of manipulating and detecting individual magnetic particles, such as spherical super-paramagnetic beads, and providing biosensing functionality. The platform is implemented in an integrated circuit, a portion of the surface of which is functionalized with one or more biochemical agents that binds tightly (i.e., specifically) with a target analyte. The magnetic beads are similarly functionalized with one or more biochemical agents that that bind specifically with the target analyte. When a sample is introduced, magnetic beads that specifically bind to the integrated circuit can be separated from non-specifically bound beads and detected.

Abstract: A low-leakage circuit includes first, second, and third transistors, which may be P-channel or N-channel FETs. The first transistor provides an output current when enabled and presents low leakage current when disabled. The second transistor enables or disables the first transistor. The third transistor connects or isolates the first transistor to/from a predetermined voltage (e.g., VDD or VSS). The circuit may further include a pass transistor that provides a reference voltage to the source of the first transistor when the first transistor is disabled. In an ON state, the first transistor provides the output current, and the second and third transistors do not impact performance. In an OFF state, the second and third transistors are used to provide appropriate voltages to the first transistor to place it in a low-leakage state. The first, second, and third transistors may be used for a low-leakage current source within a current mirror, an amplifier stage, and so on.

Abstract: A PLL includes a charge pump, a loop filter, a VCO, and a calibration unit. The calibration unit performs coarse tuning to select one or multiple frequency ranges, performs fine tuning to determine an initial control voltage that puts the VCO near a desired operating frequency, measures the VCO gain at different control voltages, and derives VCO gain compensation values for the different control voltages. The calibration unit also pre-charges the loop filter to the initial control voltage to shorten acquisition time, enables the loop filter to drive the VCO to lock to the desired operating frequency, and performs VCO gain compensation during normal operation. For VCO gain compensation, the calibration unit measures the control voltage, obtains the VCO gain compensation value for the measured control voltage, and adjusts the gain of at least one circuit block (e.g., the charge pump) to account for variation in the VCO gain.

Abstract: Provided are a method, system, and program for a model publishing framework. An intermediate data structure is generated from a model to include elements providing information on the model, wherein the model defines an object oriented program design. A publisher registry has a plurality of registered publishers. One registered publisher is selected from the publisher registry to use to publish the model. The publisher includes formatting information to generate model output. The selected publisher accesses the intermediate data structure and generates output from the elements in the intermediate data structure according to the formatting information to provide a visualization of the defined model.

Abstract: A low-leakage circuit includes first, second, and third transistors, which may be P-channel or N-channel FETs. The first transistor provides an output current when enabled and presents low leakage current when disabled. The second transistor enables or disables the first transistor. The third transistor connects or isolates the first transistor to/from a predetermined voltage (e.g., VDD or VSS). The circuit may further include a pass transistor that provides a reference voltage to the source of the first transistor when the first transistor is disabled. In an ON state, the first transistor provides the output current, and the second and third transistors do not impact performance. In an OFF state, the second and third transistors are used to provide appropriate voltages to the first transistor to place it in a low-leakage state. The first, second, and third transistors may be used for a low-leakage current source within a current mirror, an amplifier stage, and so on.

Abstract: A PLL includes a charge pump, a loop filter, a VCO, and a calibration unit. The calibration unit performs coarse tuning to select one or multiple frequency ranges, performs fine tuning to determine an initial control voltage that puts the VCO near a desired operating frequency, measures the VCO gain at different control voltages, and derives VCO gain compensation values for the different control voltages. The calibration unit also pre-charges the loop filter to the initial control voltage to shorten acquisition time, enables the loop filter to drive the VCO to lock to the desired operating frequency, and performs VCO gain compensation during normal operation. For VCO gain compensation, the calibration unit measures the control voltage, obtains the VCO gain compensation value for the measured control voltage, and adjusts the gain of at least one circuit block (e.g., the charge pump) to account for variation in the VCO gain.

Abstract: Techniques for compensating for propagation delay differences between signals distributed within a logic circuit. A delay matching circuit mimics the internal clock-to-Q delay produced by a flop. The delay matching circuit is placed in the propagation path of an original signal, such as a clock signal, to be redistributed. In general, the delay matching circuit may include a propagation gate multiplexer have a particular configuration. The delay matching circuit imposes a delay substantially equal to the clock-to-Q delay experienced by divided versions of the original signal. In this manner, the delay matching circuit ensures that the rising and falling edges of the original signal and the divided signal are in substantial alignment, enabling synchronous operation. Hence, the delay matching circuit is capable of synchronizing the redistributed and divided signals.

Abstract: Techniques for compensating for propagation delay differences between signals distributed within a logic circuit. A delay matching circuit mimics the internal clock-to-Q delay produced by a flop. The delay matching circuit is placed in the propagation path of an original signal, such as a clock signal, to be redistributed. In general, the delay matching circuit may include a propagation gate multiplexer have a particular configuration. The delay matching circuit imposes a delay substantially equal to the clock-to-Q delay experienced by divided versions of the original signal. In this manner, the delay matching circuit ensures that the rising and falling edges of the original signal and the divided signal are in substantial alignment, enabling synchronous operation. Hence, the delay matching circuit is capable of synchronizing the redistributed and divided signals.

Abstract: Techniques for compensating for propagation delay differences between signals distributed within a logic circuit. A delay matching circuit mimics the internal clock-to-Q delay produced by a flop. The delay matching circuit is placed in the propagation path of an original signal, such as a clock signal, to be redistributed. In general, the delay matching circuit may include a propagation gate multiplexer have a particular configuration. The delay matching circuit imposes a delay substantially equal to the clock-to-Q delay experienced by divided versions of the original signal. In this manner, the delay matching circuit ensures that the rising and falling edges of the original signal and the divided signal are in substantial alignment, enabling synchronous operation. Hence, the delay matching circuit is capable of synchronizing the redistributed and divided signals.

Abstract: Techniques for compensating for propagation delay differences between signals distributed within a logic circuit. A delay matching circuit mimics the internal clock-to-Q delay produced by a flop. The delay matching circuit is placed in the propagation path of an original signal, such as a clock signal, to be redistributed. In general, the delay matching circuit may include a propagation gate multiplexer have a particular configuration. The delay matching circuit imposes a delay substantially equal to the clock-to-Q delay experienced by divided versions of the original signal. In this manner, the delay matching circuit ensures that the rising and falling edges of the original signal and the divided signal are in substantial alignment, enabling synchronous operation. Hence, the delay matching circuit is capable of synchronizing the redistributed and divided signals.