Abstract: A method of fabricating an electrical contact through a through hole in a substrate, wherein the through hole is at least in part filled with a liquid conductive material and the solidified liquid conductive material provides an electrical contact through the through hole.

Abstract: In a method of making an electronic component, an electrically conductive redistribution line is formed on a surface of a semiconductor chip. The redistribution line includes a solder pad. A covering material is formed over the solder pad and an uncovered portion of the redistribution line is passivated. The covering material prevents passivation of the solder pad. Solder is then formed over the solder pad such that the uncovered portion of the redistribution line has solder resist properties due to the passivating.

Abstract: Structures for signal distribution are produced by applying a metallic seed layer over a semiconductor body. An insulating layer is applied over the metallic seed layer and openings in the insulating layer are produced by photolithographic patterning of the insulating layer. Each opening in the insulating layer is trapezoidal in cross section such that an upper portion of the insulating layer is wider than a lower portion of the insulating layer. A conductor is selectively formed over exposed portions of the metallic seed layer. After selectively forming the conductor, the insulating layer is anisotropically etched such that portions of the insulating layer abutting sidewalls of the conductor remain. Alternatively, a second insulating layer can be formed and anisotropically etched.

Abstract: The invention relates to a method for producing a rewiring printed circuit board with a substrate wafer having passage connections between a first and a second surface. One embodiment of the method comprises applying and patterning masking layers on the first and the second surfaces, thereby uncovering a first contact location on the first surface and a second contact location on the second surface; applying a protective layer to the second surface in order to protect the corresponding masking layer and the second contact location during subsequent method steps; applying a first conductor structure to the first surface, the first conductor structure on the first surface covering the first contact location; removing the protective layer on the second surface; and applying a second conductor structure to the second surface, the second conductor structure on the second surface covering the second contact location.

Abstract: An electronic component includes compliant elevations having electrical contact areas for contact-connecting the component to an electronic circuit. The compliant elevations are arranged on a surface of the component and the electrical contact areas are arranged on the tip of the compliant elevations. The electrical contact with the electronic circuit is embodied by means of electrical conductive tracks arranged on the surface of the component. The conductive tracks ascend on the outer surfaces of the compliant elevations to the electrical contact areas.

Abstract: The invention relates to a method for improving the mechanical properties of BOC module arrangements in which chips have 3D structures, solder balls, ? springs or soft bumps which are mechanically and electrically connected by means of solder connections to terminal contacts on a printed circuit board or leadframe. Advantages are achieved by providing a casting compound for the wafer or the chips after they have been individually separated and before they are mounted on the printed circuit board in such a way that the tips of the 3D structures protrude from this compound. The casting compound preferably has elastic and mechanical properties comparable to those of silicon.

Abstract: A method of fabricating an electrical contact through a through hole in a substrate, wherein the through hole is at least in part filled with a liquid conductive material and the solidified liquid conductive material provides an electrical contact through the through hole.

Abstract: In a method of making an electronic component, an electrically conductive redistribution line is formed on a surface of a semiconductor chip. The redistribution line includes a solder pad. A covering material is formed over the solder pad and an uncovered portion of the redistribution line is passivated. The covering material prevents passivation of the solder pad. Solder is then formed over the solder pad such that the uncovered portion of the redistribution line has solder resist properties due to the passivating.

Abstract: A process produces metallic interconnects and contact surfaces on electronic components using a copper-nickel-gold layer structure. The copper core of the interconnects and contact surfaces is deposited by electroplating by means of a first resist mask made from positive resist. The copper core of the interconnects and contact surfaces is surrounded by a nickel-gold layer by means of a second resist mask. The interconnects and contact surfaces are produced by means of two resist masks arranged one on top of the other, in such a way that the copper which forms the core of the interconnect is completely surrounded by the nickel-gold layer, which extends above the copper core, and an adjoining layer that extends beneath the copper core and comprises a diffusion barrier and seed layer.

Abstract: An arrangement for protecting fuses/anti-fuses on chips which serve to activate redundant circuits or chip functions includes a passivation layer (e.g., hard passivation) arranged on a fully processed chip with the exception of metal contacts of a metallization level and the fuses. The chip is provided with a redistribution layer that is electrically contact-connected to the metallization level, and to a process for protecting such fuses/anti-fuses. The invention is now based on the object of ensuring sufficient protection of fuses/anti-fuses on integrated circuits. This is achieved by virtue of the fact that a dielectric (3.1, 3.2), which covers at least the region of the fuses/anti-fuses (4) and to which the redistribution layer (2) comprising the combination of materials Cu/Ni/Au is applied, is arranged on the passivation layer (5).

Abstract: The invention, which relates to a method for fabricating metallic interconnects with copper-nickel-gold layer construction on electronic components, is based on the object of specifying a method by means of which it is possible to fabricate such metallic interconnects on different electronic components cost-effectively by means of the known and tried and tested methods which have a comprehensive corrosion protection. According to the invention, the object is achieved by virtue of the fact that the interconnects are embodied such that they are completely encapsulated by being deposited in a manner buried in a patterned dielectric layer in the lower region and being covered in the upper region by a nickel-gold layer adjoining the lower encapsulation without any gaps.

Abstract: A conductive connection is made between a semiconductor chip and an external conductor structure. An elevation element is applied on the surface of the semiconductor chip and a soldering island is arranged on the elevation element. An interconnect is produced below the soldering island as far as a bonding island or an I/O pad. Increased reliability of conductive connections of the bonding island or the I/O pad to an external conductive structure can be achieved by preventing the flowing-away of the solder and the oxidation or corrosion of the conductive layer.

Abstract: The invention relates to a method and arrangement for assembling and packaging single and multiple semiconductor dice with an intermediate arranged interposer. The interposer is arranged onto the backside of a die within the wafer composite and thereby during the wafer level process. Preferably the interposer is printed by a stencil printing process.

Abstract: The invention relates to a method for protecting the redistribution layer on wafers/chips, which preferably comprises a structure constructed from a seed layer, a layer of copper situated on the seed layer, a nickel layer arranged thereon, and a gold layer covering the latter. The wafer (4) provided with the redistribution layer (1) is covered on its entire surface with an organic protective layer (12), e.g., made of BTA (benzotriazole), Glicoat or Preventol®, which protects the redistribution layer (1) from corrosion and oxidation in that it produces a dense covering of the metal surface of the redistribution layer (1) through chemical bonding.

Abstract: The invention relates to a method for producing a rewiring printed circuit board with a substrate wafer having passage connections between a first and a second surface. One embodiment of the method comprises applying and patterning masking layers on the first and the second surfaces, thereby uncovering a first contact location on the first surface and a second contact location on the second surface; applying a protective layer to the second surface in order to protect the corresponding masking layer and the second contact location during subsequent method steps; applying a first conductor structure to the first surface, the first conductor structure on the first surface covering the first contact location; removing the protective layer on the second surface; and applying a second conductor structure to the second surface, the second conductor structure on the second surface covering the second contact location.

Abstract: An arrangement reduces the electrical crosstalk on a chip, in particular between adjacent conductors of the redistribution routing and/or between the redistribution routing on the first passivation on the chip and the metallization of the chip. In one aspect, the arrangement reduces the crosstalk between the redistribution wiring on a chip and its metallization and can be realized simply and independently at the front end. This is achieved by at least an additional conductor (10) being respectively arranged between adjacent conductors of the redistribution routing (1) and/or at least a second passivation (7) with a lower dielectric constant of a preferred “cold dielectric” being arranged between the redistribution routing (1) and the first passivation (2) on the active region of the chip (3).

Abstract: A semiconductor device includes a semiconductor chip with a plurality of bonding pads at an upper surface and a passivation layer overlying the upper surface. A rewiring layer electrically coupling ones of the bonding pads to corresponding ones of a plurality of contact pads. The rewiring layer is formed by forming a first conductor and forming a covering layer of a precious metal over the first conductor. After forming the rewiring layer, a portion of the precious metal is removed from over the first conductor between the contact pads and bonding pads.

Abstract: An arrangement for protecting fuses/anti-fuses on chips which serve to activate redundant circuits or chip functions includes a passivation layer (e.g., hard passivation) arranged on a fully processed chip with the exception of metal contacts of a metallization level and the fuses. The chip is provided with a redistribution layer that is electrically contact-connected to the metallization level, and to a process for protecting such fuses/anti-fuses. The invention is now based on the object of ensuring sufficient protection of fuses/anti-fuses on integrated circuits. This is achieved by virtue of the fact that a dielectric (3.1, 3.2), which covers at least the region of the fuses/anti-fuses (4) and to which the redistribution layer (2) comprising the combination of materials Cu/Ni/Au is applied, is arranged on the passivation layer (5).

Abstract: Structures for signal distribution are produced by applying a metallic seed layer over a semiconductor body. An insulating layer is applied over the metallic seed layer and openings in the insulating layer are produced by photolithographic patterning of the insulating layer. Each opening in the insulating layer is trapezoidal in cross section such that an upper portion of the insulating layer is wider than a lower portion of the insulating layer. A conductor is selectively formed over exposed portions of the metallic seed layer. After selectively forming the conductor, the insulating layer is anisotropically etched such that portions of the insulating layer abutting sidewalls of the conductor remain. Alternatively, a second insulating layer can be formed and anisotropically etched.

Abstract: The invention, which relates to a method for fabricating metallic interconnects with copper-nickel-gold layer construction on electronic components, is based on the object of specifying a method by means of which it is possible to fabricate such metallic interconnects on different electronic components cost-effectively by means of the known and tried and tested methods which have a comprehensive corrosion protection. According to the invention, the object is achieved by virtue of the fact that the interconnects are embodied such that they are completely encapsulated by being deposited in a manner buried in a patterned dielectric layer in the lower region and being covered in the upper region by a nickel-gold layer adjoining the lower encapsulation without any gaps.