Abstract: Systems, apparatuses, and methods are provided for write abort detection. A memory system may write data to one or more cells in a memory. An abrupt shutdown may interrupt the write, resulting in an uncertainty as to the state of the memory cells. In order to determine the state of the memory cells, after power-up, a first section of memory that includes the memory cells is analyzed, such as counting values of logic “0”s stored in the memory cells of the first section of memory. However, the values in the first section of memory may be subject to error, hindering the accuracy of write abort detection. In order to reduce or cancel the effect of the errors, a second section of memory (which may suffer from similar errors as the first section) is analyzed, such as by counting values of logic “0”s stored in the memory cells of the second section of memory.