Patents by Inventor Oded Norman

Oded Norman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7725513
    Abstract: The present invention provides techniques for efficiently determining a minimum or maximum of a plurality of values and the index of the minimum using registers of a processor. The present invention also provides for various processor instructions for determining the minimum/maximum and index of two or more values. The present invention finds particular benefit in implementing heaps and in systems utilizing Weighted Fair Queuing (WFQ).
    Type: Grant
    Filed: January 15, 2004
    Date of Patent: May 25, 2010
    Assignee: Ikanos Communications, Inc.
    Inventors: Boris Zabarski, David Sitbon, Oded Norman
  • Publication number: 20070255903
    Abstract: Devices, systems and methods of accessing a memory. For example, an apparatus includes: at least one buffer to store a data line read from a memory; and gatherer to store at least a portion of said data line and at least a portion of a previously read data line stored in said at least one buffer.
    Type: Application
    Filed: May 1, 2006
    Publication date: November 1, 2007
    Inventors: Meir Tsadik, Oded Norman, Ron Gabor
  • Publication number: 20070192572
    Abstract: The present invention provides techniques for efficiently determining a minimum or maximum of a plurality of values and the index of the minimum using registers of a processor. The present invention also provides for various processor instructions for determining the minimum/maximum and index of two or more values. The present invention finds particular benefit in implementing heaps and in systems utilizing Weighted Fair Queuing (WFQ).
    Type: Application
    Filed: April 3, 2007
    Publication date: August 16, 2007
    Applicant: CONEXANT SYSTEMS, INC.
    Inventors: Boris Zabarski, David Sitbon, Oded Norman
  • Publication number: 20040148320
    Abstract: The present invention provides techniques for efficiently determining a minimum or maximum of a plurality of values and the index of the minimum using registers of a processor. The present invention also provides for various processor instructions for determining the minimum/maximum and index of two or more values. The present invention finds particular benefit in implementing heaps and in systems utilizing Weighted Fair Queuing (WFQ).
    Type: Application
    Filed: January 15, 2004
    Publication date: July 29, 2004
    Applicant: Globespan Virata Incorporated
    Inventors: Boris Zabarski, David Sitbon, Oded Norman
  • Patent number: 6687813
    Abstract: A data processing system has a pipelined architecture and looping capability that allows a sequence of instruction execution sets to be repeated N times. The data processing system has an internal memory module data arithmetic logic units, and a program sequencer for fetching instruction fetch sets, dispatching instructions out of a instruction execution set to the data arithmetic logic units, and controlling the execution of nested loops. The instruction execution set is a subset of the instruction fetch set. The instruction execution set that initiates the conditional jump operation has a prefix instruction for initiating the conditional jump operation.
    Type: Grant
    Filed: January 21, 2000
    Date of Patent: February 3, 2004
    Assignee: Motorola, Inc.
    Inventors: Oded Norman, Gilad Hazan, Noam Benayahu
  • Patent number: 6657977
    Abstract: A radio (10) with a burst event execution and time synchronization apparatus (16) executes instructions during and after performing time synchronization between a mobile unit and a base station. Both base station (12) and mobile radio (10) have internal timer units (26, 16). Mobile radio (10) timing unit (16) is reset during synchronization between the mobile radio (10) and the base station (12). The control unit (18) writes instructions I(i) including their execution times T(i) to a memory bank (42) within the mobile radio (10). Execution logic (32) within mobile radio (10) executes instruction operands O(i) when execution time T(i) is equal or smaller then a timing count signal received from the timer unit (16). When a time synchronization reset causes the radio (10) time count to jump past queued instructions they can be executed immediately in a burst or delayed until the next communication frame.
    Type: Grant
    Filed: March 26, 1999
    Date of Patent: December 2, 2003
    Assignee: Motorola, Inc.
    Inventors: Oded Norman, Moshe Refaeli, Yoram Salant, Jean M. Khawand
  • Publication number: 20030212830
    Abstract: Systems and methods are provided for implementing: a rings architecture for communications and data handling systems; an enumeration process for automatically configuring the ring topology; automatic routing of messages through bridges; extending a ring topology to external devices; write-ahead functionality to promote efficiency; wait-till-reset operation resumption; in-vivo scan through rings topology; staggered clocking arrangement; and stray message detection and eradication. Other inventive elements conveyed include: an architectural overview of a packet processor; a programming model for a packet processor; an instruction pipeline for a packet processor; and use of a packet processor as a module on a rings-based architecture.
    Type: Application
    Filed: July 2, 2002
    Publication date: November 13, 2003
    Applicant: Globespan Virata Incorporated
    Inventors: Ilia Greenblat, Moshe Tarrab, Uri Trichter, Oded Norman, Elizer Weitz
  • Publication number: 20030200339
    Abstract: Systems and methods are provided for implementing: a rings architecture for communications and data handling systems; an enumeration process for automatically configuring the ring topology; automatic routing of messages through bridges; extending a ring topology to external devices; write-ahead functionality to promote efficiency; wait-till-reset operation resumption; in-vivo scan through rings topology; staggered clocking arrangement; and stray message detection and eradication. Other inventive elements conveyed include: an architectural overview of a packet processor; a programming model for a packet processor; an instruction pipeline for a packet processor; and use of a packet processor as a module on a rings-based architecture.
    Type: Application
    Filed: July 2, 2002
    Publication date: October 23, 2003
    Applicant: GlobespanVirata Incorporated
    Inventors: Ilia Greenblat, Moshe Tarrab, Uri Trichter, Oded Norman, Boris Zabarski, Moshe Refaeli, Elizer Weitz
  • Publication number: 20030196076
    Abstract: Systems and methods are provided for implementing: a rings architecture for communications and data handling systems; an enumeration process for automatically configuring the ring topology; automatic routing of messages through bridges; extending a ring topology to external devices; write-ahead functionality to promote efficiency; wait-till-reset operation resumption; in-vivo scan through rings topology; staggered clocking arrangement; and stray message detection and eradication. Other inventive elements conveyed include: an architectural overview of a packet processor; a programming model for a packet processor; an instruction pipeline for a packet processor; and use of a packet processor as a module on a rings-based architecture.
    Type: Application
    Filed: July 2, 2002
    Publication date: October 16, 2003
    Applicant: Globespan Virata Incorporated
    Inventors: Boris Zabarski, Moshe Tarrab, Oded Norman
  • Patent number: 6366786
    Abstract: A mobile radio (10) with a synchronization apparatus (14) executes a method (60) for time synchronizing the radio (10) and a base station (12). Base station (12) and radio (10) have internal timers (26, 16). A control unit (18) in the radio (10) receives a signal (29) from the base station (12) and determines the difference F between timers (26, 16, 30) in the base (12) and mobile (10). The control unit (18) writes instructions I(i) and their execution times T(i) to a memory (42) within the radio (10). One of these instructions I(N) reloads the radio timing counter (30) with a corrected value C=f(F,B) at a predetermined time T(N)=B which avoids conflicts with other operations of the radio (10).
    Type: Grant
    Filed: March 8, 1999
    Date of Patent: April 2, 2002
    Assignee: Motorola, Inc.
    Inventors: Oded Norman, Moshe Refaeli, Boaz Perlman, Yoram Salant, Paul McAlinden
  • Patent number: 6178332
    Abstract: A radio (10) executes a method (100) for entering and exiting a halt status. Radio (10) has a control unit (18) and an internal timing unit (16). The timing unit (16) has execution logic (32), a status register (46) a counter (30) and a clock source (37). The control unit (18) writes instructions I(i) and their execution times T(i) to a memory (42) within the execution logic (32). One of these instructions is a ‘SWITCH CLOCK’ instruction causing the timing unit (16) to switch between clock signals. One of the instructions is ‘HALT COUNTER’ causing the radio (10) to enter a halt state. The radio (10) can be synchronized to the end of a first communication frame received by it after exiting a halt state.
    Type: Grant
    Filed: March 8, 1999
    Date of Patent: January 23, 2001
    Assignee: Motorola, Inc.
    Inventors: Oded Norman, Moshe Refaeli, Boaz Perlman, Yoram Salant, Paul McAlinden
  • Patent number: 6125404
    Abstract: A communications system includes multiple processors (14, 16) and a protocol timer (18). The protocol timer (18) controls the timing of events in the communications system and operates autonomously after it is loaded with initial instructions by one of the multiple processors (14, 16). The protocol timer (18) utilizes a frame event table (50) and a macro event table (46, 48) to trigger events and to generate interrupts of the multiple processors (14, 16). By allowing the protocol timer (18) to operate autonomously, the processors (14, 16) are relieved of timing control, and can be powered down when not in use, thus reducing power consumption of the communications system. Also, by using the protocol timer (18) to control the timing of events, software related errors and interrupt latencies are reduced.
    Type: Grant
    Filed: April 17, 1998
    Date of Patent: September 26, 2000
    Assignee: Motorola, Inc.
    Inventors: John J. Vaglica, Paul McAlinden, Oded Norman, Moshe Refaeli, Yoram Salant, Thomas E. Oberhauser, Arvind Singh Arora
  • Patent number: 6076096
    Abstract: A rate multiplier for rate multiplying a pulse train comprising: an accumulator, a multiplexer for selecting one of a first and a second number of different signs to feed to the accumulator, and a pulse train gate for providing or blocking the pulse train, wherein the multiplexer and the pulse train gate are controlled by the MSB output signal of the accumulator.
    Type: Grant
    Filed: January 13, 1998
    Date of Patent: June 13, 2000
    Assignee: Motorola Inc.
    Inventors: Eyal Salomon, Yoram Salant, Oded Norman, Vladimir Koifman
  • Patent number: 5628026
    Abstract: To execute a three-dimensional DMA transfer, a transfer counter register (76), which is partitioned into three sections, is loaded with initial counter values. Each section of the counter register (76) is independently controlled by a counter (72, 73, 74). Data is transferred from consecutive generated addresses for a first predetermined number of times as determined by the value in the first section of the counter register (76). An offset value is then added to a last generated address. The process is repeated for a second predetermined number of times. Then another offset value is added to the generated address. This entire process is repeated for a given number of times as determined by the third section of the register (76). The initial counter values are reloaded into counter register (76) from a backup register (77), insuring that a DMA controller (80) is ready if a new transfer request requires the same counter values as the previous transfer.
    Type: Grant
    Filed: December 5, 1994
    Date of Patent: May 6, 1997
    Assignee: Motorola, Inc.
    Inventors: Natan Baron, Eliezer Zand, Oded Norman, Zvika Rozenshein, Elchanan Rushinek