Patents by Inventor Oded SCHWARTZ

Oded SCHWARTZ has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250139195
    Abstract: A computer-implemented method comprising: receiving, as input, matrices A, B and a linear combination of blocks for a main multiplications operation with respect to the input matrices A, B; applying an inner matrix multiplication algorithm to calculate separately: (i) the main multiplications of input matrices A, B, using the linear combination of blocks, (ii) correction terms for the input matrix A, and (iii) correction terms for the input matrix B; and combining the results of the calculating, to obtain a matrix multiplication operation result C of the input matrices A, B.
    Type: Application
    Filed: February 3, 2023
    Publication date: May 1, 2025
    Inventors: Oded SCHWARTZ, Yoav MORAN
  • Publication number: 20250013718
    Abstract: A computer-implemented method comprising: receiving two or more input matrices for a multiplication operation; determining, for each of the input matrices, a series of transformations, and applying the series of transformations respectively to the input matrices to obtain transformed the input matrices, wherein each of the series of transformations reduces a number of arithmetic operations required to perform the multiplication operation, given a desired value of communication costs required to perform the multiplication operation using the computer system, and wherein each of the series of transformations is performed over two or more recursions, wherein at least one of the recursions comprises at least two the transformations; applying a recursive bilinear computation to the transformed two or more input matrices, thereby producing a transformed multiplied matrix; and determining an output series of transformations which are applied to the transformed multiplied matrix, to obtain a product of the input matr
    Type: Application
    Filed: August 26, 2024
    Publication date: January 9, 2025
    Inventors: Oded SCHWARTZ, Yoav MORAN, Noa VAKNIN
  • Publication number: 20220147595
    Abstract: A system comprising: at least one hardware processor; and a non-transitory computer-readable storage medium having program instructions embodied therewith, the program instructions executable by said at least one hardware processor to: receive a first matrix and a second matrix, compute a first transformation of said first matrix, to obtain a transformed said first matrix, compute a second transformation of said second matrix, to obtain a transformed said second matrix, apply a bilinear computation to said transformed first matrix and said transformed second matrix, thereby producing a transformed multiplied matrix; and apply a third transformation to said transformed multiplied matrix, to obtain a product of said first and second matrices, wherein at least one of said first, second, and third transformations is a non-homomorphic transformation into a linear space of any intermediate dimension.
    Type: Application
    Filed: March 12, 2020
    Publication date: May 12, 2022
    Inventors: Oded SCHWARTZ, Gal BENIAMINI
  • Patent number: 11080131
    Abstract: A computer implemented method for performing fault tolerant numerical linear algebra computation task consisting of calculation steps that include at least classic or fast matrix multiplication, according to which, a controller splits the task among P processors, which operate in parallel. Additional processors are assigned according to execution and resources parameters, which are also used to select a slice-coded recovery algorithm or a posterior-recovery algorithm for executing the task. Pipelined-reduce operations are used to generate error correcting codes to protect the input blocks and outer products from faults. Upon detecting faults in one or more processors, if the slice-coded recovery algorithm has been selected, a slice-coded recovery algorithm is executed to recover lost input blocks and outer products that.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: August 3, 2021
    Assignee: Yissum Research Development Company of The Hebrew University of Jerusalem Ltd.
    Inventors: Oded Schwartz, Noam Birnbaum
  • Patent number: 10387534
    Abstract: A computerized method comprising operating one or more hardware processor for receiving a first matrix and a second matrix. The hardware processor(s) are operated for determining a basis transformation, wherein the basis transformation is invertible to an inverted basis transformation. The hardware processor(s) are operated for computing an alternative basis first matrix by multiplying the first matrix by the basis transformation. The hardware processor(s) are operated for computing an alternative basis second matrix by multiplying the second matrix by the basis transformation. The hardware processor(s) are operated for performing a matrix multiplication of the alternative basis first matrix and the alternative basis second matrix, thereby producing an alternative basis multiplied matrix. The hardware processor(s) are operated for computing a multiplied matrix by multiplying the alternative basis multiplied matrix by the inverted basis transformation.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: August 20, 2019
    Assignee: YISSUM RESEARCH DEVELOPMENT COMPANY OF THE HEBREW UNIVERSITY OF JERUSALEM LTD.
    Inventors: Oded Schwartz, Elaye Karstadt
  • Publication number: 20180365099
    Abstract: A computer implemented method for performing fault tolerant numerical linear algebra computation task consisting of calculation steps that include at least classic or fast matrix multiplication, according to which, a controller splits the task among P processors, which operate in parallel. Additional processors are assigned according to execution and resources parameters, which are also used to select a slice-coded recovery algorithm or a posterior-recovery algorithm for executing the task. Pipelined-reduce operations are used to generate error correcting codes to protect the input blocks and outer products from faults. Upon detecting faults in one or more processors, if the slice-coded recovery algorithm has been selected, a slice-coded recovery algorithm is executed to recover lost input blocks and outer products that.
    Type: Application
    Filed: June 18, 2018
    Publication date: December 20, 2018
    Inventors: Oded Schwartz, Noam Birnbaum
  • Publication number: 20180150431
    Abstract: A computerized method comprising operating one or more hardware processor for receiving a first matrix and a second matrix. The hardware processor(s) are operated for determining a basis transformation, wherein the basis transformation is invertible to an inverted basis transformation. The hardware processor(s) are operated for computing an alternative basis first matrix by multiplying the first matrix by the basis transformation. The hardware processor(s) are operated for computing an alternative basis second matrix by multiplying the second matrix by the basis transformation. The hardware processor(s) are operated for performing a matrix multiplication of the alternative basis first matrix and the alternative basis second matrix, thereby producing an alternative basis multiplied matrix. The hardware processor(s) are operated for computing a multiplied matrix by multiplying the alternative basis multiplied matrix by the inverted basis transformation.
    Type: Application
    Filed: November 28, 2017
    Publication date: May 31, 2018
    Inventors: Oded SCHWARTZ, Elaye KARSTADT