Abstract: Disclosed embodiments include system including a hardware based, programmable data analytics processor configured to reside between a data storage unit and one or more hosts. The programmable data analytics processor includes a selector module configured to input a first set of data and, based on a selection indicator, output a first subset of the first set of data; a filter and project module configured to input a second set of data and, based on a function, output an updated second set of data; a join and group module configured to combine data from one or more third data sets into a combined data set; and a communications fabric configured to transfer data between any of the selector module, the filter and project module, and the join and group module.

Abstract: A microprocessor includes a function-specific architecture, an interface configured to communicate with an external memory via at least one memory channel, a first architecture block configured to perform a first task associated with a thread, and a second architecture block configured to perform a second task associated with the thread. The second task includes a memory access via the at least one memory channel. The microprocessor further includes a third architecture block configured to perform a third task associated with the thread. The first architecture block, the second architecture block, and the third architecture block are configured to operate in parallel such that the first task, the second task, and the third task are all completed during a single clock cycle associated with the microprocessor.

Abstract: A microprocessor includes a function-specific architecture, an interface configured to communicate with an external memory via at least one memory channel, a first architecture block configured to perform a first task associated with a thread, and a second architecture block configured to perform a second task associated with the thread. The second task includes a memory access via the at least one memory channel. The microprocessor further includes a third architecture block configured to perform a third task associated with the thread. The first architecture block, the second architecture block, and the third architecture block are configured to operate in parallel such that the first task, the second task, and the third task are all completed during a single clock cycle associated with the microprocessor.

Abstract: Disclosed embodiments include system including a hardware based, programmable data analytics processor configured to reside between a data storage unit and one or more hosts. The programmable data analytics processor includes a selector module configured to input a first set of data and, based on a selection indicator, output a first subset of the first set of data; a filter and project module configured to input a second set of data and, based on a function, output an updated second set of data; a join and group module configured to combine data from one or more third data sets into a combined data set; and a communications fabric configured to transfer data between any of the selector module, the filter and project module, and the join and group module.

Abstract: A data pre-processing architecture may include an interface and a pruning logic configured to receive, via the interface, at least one filter value from a query processor; use the at least one filter value to scan rows or columns of a data table stored in a memory; generate a selection indicator identifying a set of rows or columns of the data table where the at least one filter value resides; and provide to the query processor a filtered output based on the selection indicator.

Abstract: In one embodiment, an apparatus includes n electrical communication channels, m optical communication media interfaces, and a plurality of muxes. The plurality of muxes are configured to receive an information stream. The information stream is carried over the n electrical communication channels and the m optical communication media interfaces. The plurality of muxes are further configured to transform the information stream from v virtual lanes. Each virtual lane includes a plurality of data blocks from the information stream and an alignment block, wherein v is a positive integer multiple of the least common multiple of m and n, v is greater than n, and n is equal to m.

Abstract: In one embodiment, an apparatus includes n electrical communication channels, m optical communication media interfaces, and a plurality of muxes. The plurality of muxes are configured to receive an information stream. The information stream is carried over the n electrical communication channels and the m optical communication media interfaces. The plurality of muxes are further configured to transform the information stream from v virtual lanes. Each virtual lane includes a plurality of data blocks from the information stream and an alignment block, wherein v is a positive integer multiple of the least common multiple of m and n, v is greater than n, and n is equal to m.

Abstract: In one embodiment, an apparatus includes n electrical communication channels, m optical communication media interfaces, and a plurality of muxes. The plurality of muxes are configured to receive an information stream, the information stream carried over the n electrical communication channels and the m optical communication media interfaces. The plurality of muxes are further configured to transform the information stream from v virtual lanes, each virtual lane comprising a plurality of data blocks from the information stream and an alignment block, wherein v is a positive integer multiple of the least common multiple of m and n.

Abstract: Techniques for reducing latency associated with metaframe error correction. Embodiments receive, via a first port of a plurality of ports, a stream of bits within a metaframe. Upon evaluating a first cyclic redundancy check (CRC) for a first portion of the stream of bits and determining that the first CRC is valid, a measure of latency incurred in transmitting the first portion is reduced, relative to first performing forward error correction (FEC) decoding for the first portion prior to transmission, by transmitting the first portion of the stream of bits without performing FEC decoding for the first portion of the stream of bits. Upon evaluating a second CRC for a second portion of the stream of bits and determining that the second CRC is invalid, FEC decoding is performed for the second portion of the stream of bits before forwarding the second portion of the stream of bits.

Abstract: In one embodiment, an apparatus includes n electrical communication channels, m optical communication media interfaces, and a plurality of muxes. The plurality of muxes are configured to receive an information stream, the information stream carried over the n electrical communication channels and the m optical communication media interfaces. The plurality of muxes are further configured to transform the information stream from v virtual lanes, each virtual lane comprising a plurality of data blocks from the information stream and an alignment block, wherein v is a positive integer multiple of the least common multiple of m and n.

Abstract: An apparatus is provided that includes communication channels, and m communication media interfaces, and v virtual lanes. V is a positive integer multiple of the least common multiple of m and n. An information stream is transferred into data and alignment blocks striped across all of the v virtual lanes, the blocks being communicated from the virtual lanes onto the communication channels. The blocks are received on the communication channels. Each of the communication channels transmits a different portion of the blocks striped across all of the v virtual lanes. In more particular embodiments, v>=n>=m. The communication media interfaces can be electrical and optical. Each of the communication channels can include a SerDes interface operating at least 5 Gigabits per second. Furthermore, each of the m communication media interfaces is configured to transmit a different stream of information over a single optical fiber.

Abstract: Techniques for reducing latency associated with metaframe error correction. Embodiments receive, via a first port of a plurality of ports, a stream of bits within a metaframe. Upon evaluating a first cyclic redundancy check (CRC) for a first portion of the stream of bits and determining that the first CRC is valid, a measure of latency incurred in transmitting the first portion is reduced, relative to first performing forward error correction (FEC) decoding for the first portion prior to transmission, by transmitting the first portion of the stream of bits without performing FEC decoding for the first portion of the stream of bits. Upon evaluating a second CRC for a second portion of the stream of bits and determining that the second CRC is invalid, FEC decoding is performed for the second portion of the stream of bits before forwarding the second portion of the stream of bits.

Abstract: Embodiments generally provide techniques for data framing and error correction for communications on a link. Embodiments include receiving a stream of bits within a metaframe. Upon determining that a cyclic redundancy check (CRC) for a portion of the stream of bits is valid, the portion of the stream of bits is forwarded without performing forward error correction (FEC) decoding for the first portion. Upon determining that a CRC for the portion of the stream of bits is invalid, FEC decoding is performed for the portion before forwarding the portion of the stream of bits. Embodiments also include generating a metaframe for transmission over a link, and upon determining that a current measure of network throughput is less than a predefined threshold amount of network throughput, inserting one or more checkpoints into the metaframe to create different segments of the metaframe. The metaframe is then transmitted over the link.

Abstract: An apparatus is provided that includes n communication channels, and m communication media interfaces, and v virtual lanes. V is a positive integer multiple of the least common multiple of m and n. An information stream is transferred into data and alignment blocks striped across all of the v virtual lanes, the blocks being communicated from the virtual lanes onto the communication channels. The blocks are received on the communication channels. Each of the communication channels transmits a different portion of the blocks striped across all of the v virtual lanes. In more particular embodiments, v>=n>=m. The communication media interfaces can be electrical and optical. Each of the communication channels can include a SerDes interface operating at least 5 Gigabits per second. Furthermore, each of the m communication media interfaces is configured to transmit a different stream of information over a single optical fiber.

Abstract: Embodiments generally provide techniques for minimizing latency and/or power consumption for communications on a link. Embodiments include receiving a stream of bits within a metaframe. Upon determining that a cyclic redundancy check (CRC) for a portion of the stream of bits is valid, the portion of the stream of bits is forwarded without performing forward error correction (FEC) decoding for the first portion. Upon determining that a CRC for the portion of the stream of bits is invalid, FEC decoding is performed for the portion before forwarding the portion of the stream of bits. Embodiments also include generating a metaframe for transmission over a link, and upon determining that a current measure of network throughput is less than a predefined threshold amount of network throughput, inserting one or more checkpoints into the metaframe to create different segments of the metaframe. The metaframe is then transmitted over the link.

Abstract: An apparatus is provided that includes communication channels, and m communication media interfaces, and v virtual lanes. V is a positive integer multiple of the least common multiple of m and n. An information stream is transferred into data and alignment blocks striped across all of the v virtual lanes, the blocks being communicated from the virtual lanes onto the communication channels. The blocks are received on the communication channels. Each of the communication channels transmits a different portion of the blocks striped across all of the v virtual lanes. In more particular embodiments, v>=n>=m. The communication media interfaces can be electrical and optical. Each of the communication channels can include a SerDes interface operating at least 5 Gigabits per second. Furthermore, each of the m communication media interfaces is configured to transmit a different stream of information over a single optical fiber.

Abstract: To calculate sequential CRCs, a CRC pipeline may be used to calculate the sequential CRCs for a block of data The CRC pipeline includes a plurality of stages, where, in each subsequent stage a CRC calculated from a previous stage is used to calculate an offset CRC. For example, using at least one CRC calculator and CRC shifter, a stage in the pipeline removes an effect of first portion of the data represented by a previously calculated CRC from the CRC and then adds an effect of a second portion of data neighboring the first portion in a received data block to yield an offset CRC. For example, a stage may change CRC(0:63) to CRC(32:95) by removing the effect of bytes 0:31 and adding the effect of bytes 64:95. At each stage, the byte offset may get smaller until all the sequential CRCs have been calculated.

Abstract: To calculate sequential CRCs, a CRC pipeline may be used to calculate the sequential CRCs for a block of data The CRC pipeline includes a plurality of stages, where, in each subsequent stage a CRC calculated from a previous stage is used to calculate an offset CRC. For example, using at least one CRC calculator and CRC shifter, a stage in the pipeline removes an effect of first portion of the data represented by a previously calculated CRC from the CRC and then adds an effect of a second portion of data neighboring the first portion in a received data block to yield an offset CRC. For example, a stage may change CRC(0:63) to CRC(32:95) by removing the effect of bytes 0:31 and adding the effect of bytes 64:95. At each stage, the byte offset may get smaller until all the sequential CRCs have been calculated.

Abstract: An apparatus is provided that includes n communication channels, and m communication media interfaces, and v virtual lanes. V is a positive integer multiple of the least common multiple of m and n. An information stream is transferred into data and alignment blocks striped across all of the v virtual lanes, the blocks being communicated from the virtual lanes onto the communication channels. The blocks are received on the communication channels. Each of the communication channels transmits a different portion of the blocks striped across all of the v virtual lanes. In more particular embodiments, v>=n>=m. The communication media interfaces can be electrical and optical. Each of the communication channels can include a SerDes interface operating at least 5 Gigabits per second. Furthermore, each of the m communication media interfaces is configured to transmit a different stream of information over a single optical fiber.

Abstract: An apparatus is provided that includes n communication channels, and m communication media interfaces, and v virtual lanes. V is a positive integer multiple of the least common multiple of m and n. An information stream is transferred into data and alignment blocks striped across all of the v virtual lanes, the blocks being communicated from the virtual lanes onto the communication channels. The blocks are received on the communication channels. Each of the communication channels transmits a different portion of the blocks striped across all of the v virtual lanes. In more particular embodiments, v>=n>=m. The communication media interfaces can be electrical and optical. Each of the communication channels can include a SerDes interface operating at least 5 Gigabits per second. Furthermore, each of the m communication media interfaces is configured to transmit a different stream of information over a single optical fiber.