Abstract: Disclosed herein is a new paradigm for qubit control using clock multipliers and dual sampling rate direct synthesis to avoid Nyquist zone gaps while covering a wide spectrum without using any synthesizer that compromises the phase noise. This system and method for multi-Nyquist direct synthesis qubit control using clock multipliers and double sampling rate is scalable to thousands of RF channels synchronized to the picosecond level.

Abstract: In a quantum computer, quantum algorithms are performed by exciting a qubit with a quantum control pulse. This quantum control pulse is an electromagnetic RF signal that is generated at baseband according to an analog waveform. An application digitally generates samples of this analog waveform using multiple classical processors that control multiple physical channels in parallel.

Abstract: Disclosed herein is a new system and method for loading quantum processor programs. Pulse processors are programmed, in real-time, according to a low-level instruction set to produce microwave pulses that manipulate the states in a quantum processor. The nature of qubits in the quantum processor causes quantum hardware characteristics to drift over time. These qubits undergo small physical changes that may damage the accuracy of the quantum gates, typically due to variation of temperature, or energy in the quantum hardware. This new system and method for loading quantum processor programs enables qubit calibration and the adjustment of the quantum hardware in real-time according to immediate feedback from one program to another.

Abstract: Disclosed herein is a new paradigm for qubit control using clock multipliers and dual sampling rate direct synthesis to avoid Nyquist zone gaps while covering a wide spectrum without using any synthesizer that compromises the phase noise. This system and method for multi-Nyquist direct synthesis qubit control using clock multipliers and double sampling rate is scalable to thousands of RF channels synchronized to the picosecond level.

Abstract: In a quantum computer, quantum algorithms are performed by exciting a qubit with a quantum control pulse. This quantum control pulse is an electromagnetic RF signal that is generated at baseband according to an analog waveform. An application digitally generates samples of this analog waveform using multiple classical processors that control multiple physical channels in parallel.

Abstract: Systems and methods are disclosed for scaling and accelerating decentralized execution of transactions. In one implementation, transactions are divided into transaction segments. A first transaction segment is executed and relevant initialization state for the first transaction segment is determined. A second transaction segment is executed based on the execution of the first transaction segment. Based on the execution of the second transaction segment and an output of the execution of the first transaction segment, a In second initialization state is determined. The first transaction segment and the first initialization state are provided to a first execution shard. The second transaction segment and the second initialization state are provided to a second execution shard. A validation of result(s) of the transactions is received. The validation is computed based an output of the execution of the first transaction segment and an output of the execution of the second transaction segment.

Abstract: Systems and methods are disclosed for decentralized application platforms for private key management. In one implementation, an authentication request associated with a user identifier is received within a first node of a decentralized authentication network. An authentication challenge is generated in accordance with an authentication protocol associated with the user identifier. Proof of possession of an authentication credential is received in response to the authentication challenge. A verification is performed to determine that the received proof conforms to the authentication protocol. Based on a verification that the received proof conforms to the authentication protocol, an authenticated operation is initiated with respect to a share of a cryptographic key stored at the first node and associated with the user identifier. The authenticated operation is completed in conjunction with one or more other shares of the cryptographic key that satisfy a defined cryptographic threshold.

Abstract: An printed circuit board (PCB) assembly and method of assembling the same for a high-speed, short-reach communication link are described that provide a mechanism for transmitting radio frequency (RF) waves from one digital electronic component of the PCB assembly to another, where the second digital electronic component is located either on the same PCB assembly or on a second PCB assembly. The assembly includes a PCB having multiple layers and a digital electronic component supported by the PCB. At least one of the layers defines a channel that confines RF waves therein. An RF antenna in communication with the digital electronic component extends into the channel, and the RF antenna transmits RF signals generated by the digital electronic component into the channel as RF waves or receives RF waves via the channel and conveys corresponding RF signals to the digital electronic component.

Abstract: An optical component assembly is provided including a substrate. The assembly includes an optical transmitter configured to transmit an optical signal, an optical receiver configured to receive the optical signal, and an optical waveguide extending between the optical transmitter and the optical receiver. The assembly further includes a frangible region defining a first portion of the substrate and a second portion of the substrate, wherein the frangible region is configured to allow the first portion to be separated from the second portion. The assembly may be configured to be modified from a testing configuration, in which the first portion is integrally connected to the second portion via the frangible region, to an operational configuration, in which the first portion is separated from the second portion such that communication of optical signals between the optical transmitter and the optical receiver is precluded.

Abstract: Communication apparatus includes a plurality of interfaces for receiving and transmitting data packets from and to a network and a memory, which receives and stores context data with respect to multicast groups. Packet processing circuitry establishes reliable connections over the network with the receiving nodes in the multicast groups, and upon receiving from a packet source on the network an incoming unicast packet containing multicast data and containing multicast metadata that identifies a multicast group, sends an acknowledgment of the incoming unicast packet to the packet source, reads the context data from the memory with respect to the identified multicast group, and transmits multiple outgoing unicast packets containing the multicast data via respective egress interfaces to the receiving nodes in the multicast group over the reliable connections.

Abstract: A switch in a data network is configured to mediate data exchanges among network elements. The apparatus further includes a processor, which organizes the network elements into a hierarchical tree having a root node network element, vertex node network elements, and child node network elements that include leaf node network elements. The leaf node network elements are originate aggregation data and transmit the aggregation data to respective parent vertex node network elements. The vertex node network elements combine the aggregation data from at least a portion of the child node network elements, and transmit the combined aggregation data from the vertex node network elements to parent vertex node network elements. The root node network element is operative for initiating a reduction operation on the aggregation data.

Abstract: An optical component assembly is provided including a substrate. The assembly includes an optical transmitter configured to transmit an optical signal, an optical receiver configured to receive the optical signal, and an optical waveguide extending between the optical transmitter and the optical receiver. The assembly further includes a frangible region defining a first portion of the substrate and a second portion of the substrate, wherein the frangible region is configured to allow the first portion to be separated from the second portion. The assembly may be configured to be modified from a testing configuration, in which the first portion is integrally connected to the second portion via the frangible region, to an operational configuration, in which the first portion is separated from the second portion such that communication of optical signals between the optical transmitter and the optical receiver is precluded.

Abstract: An printed circuit board (PCB) assembly and method of assembling the same for a high-speed, short-reach communication link are described that provide a mechanism for transmitting radio frequency (RF) waves from one digital electronic component of the PCB assembly to another, where the second digital electronic component is located either on the same PCB assembly or on a second PCB assembly. The assembly includes a PCB having multiple layers and a digital electronic component supported by the PCB. At least one of the layers defines a channel that confines RF waves therein. An RF antenna in communication with the digital electronic component extends into the channel, and the RF antenna transmits RF signals generated by the digital electronic component into the channel as RF waves or receives RF waves via the channel and conveys corresponding RF signals to the digital electronic component.

Abstract: Communication apparatus includes a plurality of interfaces for receiving and transmitting data packets from and to a network and a memory, which receives and stores context data with respect to multicast groups. Packet processing circuitry establishes reliable connections over the network with the receiving nodes in the multicast groups, and upon receiving from a packet source on the network an incoming unicast packet containing multicast data and containing multicast metadata that identifies a multicast group, sends an acknowledgment of the incoming unicast packet to the packet source, reads the context data from the memory with respect to the identified multicast group, and transmits multiple outgoing unicast packets containing the multicast data via respective egress interfaces to the receiving nodes in the multicast group over the reliable connections.

Abstract: Apparatuses and methods are described that provide for credit based flow control in a network in which a public buffer is supported at a receiver node, where a transmitter node can control the use of the public buffer. In particular, the transmitter node determines a buffer credit value (TCRi) for each virtual lane of the transmitter node. The buffer credit value (TCRi) is negative (e.g., less than 0) in an instance in which a respective virtual lane private buffer is fully used and thus reflects a loan of credits from the public buffer. In addition, the transmitter node knows the needed buffer size per virtual lane for transmitting a packet in advance based on the round trip time (RTT) and maximum transmission unit (MTU) for the packet and is precluded from consuming more space on the public buffer than required to meet RTT.

Abstract: Communication apparatus includes an input circuit, which receives a sequence of symbols arranged in a series of data blocks, including data symbols that encode the data and forward error correction (FEC) symbols that encode an error correction code. The input circuit decodes the data encoded by the data symbols and passes the decoded data to a buffer for output to a data link layer interface irrespective of the FEC symbols. An error correction circuit receives the data and the error correction code from the input circuit, and upon detecting an error in a given data block in the series, passes the corrected data from the given data block to the buffer for output to the data link layer interface in place of the data from the given data block that the input circuit decoded and passed to the buffer.

Abstract: Apparatuses and methods are described that provide for credit based flow control in a network in which a public buffer is supported at a receiver node, where a transmitter node can control the use of the public buffer. In particular, the transmitter node determines a buffer credit value (TCRi) for each virtual lane of the transmitter node. The buffer credit value (TCRi) is negative (e.g., less than 0) in an instance in which a respective virtual lane private buffer is fully used and thus reflects a loan of credits from the public buffer. In addition, the transmitter node knows the needed buffer size per virtual lane for transmitting a packet in advance based on the round trip time (RTT) and maximum transmission unit (MTU) for the packet and is precluded from consuming more space on the public buffer than required to meet RTT.

Abstract: A method in a network element includes processing input packets using a set of two or more functions that are defined over parameters of the input packets. Each function in the set produces respective interim actions applied to the input packets and the entire set produces respective end-to-end actions applied to the input packets. An end-to-end mapping, which maps the parameters of at least some of the input packets directly to the corresponding end-to-end actions, is cached in the network element. The end-to-end mapping is queried with the parameters of a new input packet. Upon finding the parameters of the new input packet in the end-to-end mapping, an end-to-end action mapped to the found parameters is applied to the new input packet, without processing the new input packet using the set of functions.

Abstract: Communication apparatus includes an input circuit, which receives a sequence of symbols arranged in a series of data blocks, including data symbols that encode the data and forward error correction (FEC) symbols that encode an error correction code. The input circuit decodes the data encoded by the data symbols and passes the decoded data to a buffer for output to a data link layer interface irrespective of the FEC symbols. An error correction circuit receives the data and the error correction code from the input circuit, and upon detecting an error in a given data block in the series, passes the corrected data from the given data block to the buffer for output to the data link layer interface in place of the data from the given data block that the input circuit decoded and passed to the buffer.

Abstract: Communication apparatus includes a PHY interface, which is configured to receive over a communication link and to decode a sequence of symbols arranged in a series of data blocks. The PHY interface includes an error correction circuit, which when actuated, corrects errors in decoded data symbols using FEC symbols in the data blocks. The decoded data include data packets containing respective error detection codes. A memory buffers the data blocks received by the PHY interface. A data link layer interface receives the data packets from the PHY interface, checks the data packets using respective error detection codes, and upon detecting an error in a given data packet, signals the PHY interface to read from the memory at least one buffered data block that contains the given data packet while actuating the error correction circuit to correct the error using the FEC symbols in the at least one buffered data block.