Abstract: A method and apparatus (200A) are provided for multiplexing data and uplink control bitstreams on a 5G-NR uplink by generating a multiplexing configuration structure with one or more processors (201) and supplying the data and uplink control bitstreams to a multiplexing engine (214) which includes an index calculation logic circuit (212) and multiplex selector circuit (213), where the index calculation logic circuit is configured with the multiplexing configuration structure (CONFIG) to execute an iterative data-control multiplexing algorithm which generates ordered selection indices in sequential order (MUX_SEL), and where the multiplex selector circuit receives and selects m-bit sequences from the data bitstream and one or more uplink control bitstreams for output into a multiplexed output stream according to the ordered selection indices generated by the index calculation unit, where m is an integer greater than or equal to 1.

Abstract: A method and apparatus may be used to generate complex exponentials for either frequency domain or time domain applications by programming input parameter values into a complex exponential vector generator (260) having a frequency generator stage (281) and a vector phase accumulator stage (282) arranged with a vector element multiplier stage (283) to generate complex exponential phase index values (?0, ?1, . . . ?v?1) that are processed by a complex exponential generator stage (284) to output a plurality of complex exponential values (e.g., ej2??0, ej2??1, . . . ej2??v?1) that may be rearranged by a permutation unit (286) for use by vector data path.

Abstract: A method and apparatus may be used to generate complex exponentials for either frequency domain or time domain applications by programming input parameter values into a complex exponential vector generator (260) having a frequency generator stage (281) and a vector phase accumulator stage (282) arranged with a vector element multiplier stage (283) to generate complex exponential phase index values (?0, ?1, . . . ?v-1) that are processed by a complex exponential generator stage (284) to output a plurality of complex exponential values (e.g., ej2??0, ej2??1, . . . ej2??v-1) that may be rearranged by a permutation unit (286) for use by vector data path.

Abstract: A process (601-611) and implementing computer system (13) for selecting a specific logic circuit among a group of otherwise acceptable alternative circuits, as represented by prime implicant terms (607), includes determining and assigning a power consumption factor (609) to each of the alternative logic circuit implementations. In the disclosed example, the probability of switching logic states (313, 513) is determined and used as a measure of the power consumption factor associated with each of the acceptable and valid prime implicant solutions for a given logic function. From a group of acceptable prime implicant solutions, the power optimum solution is chosen (611) which has been determined to be the most likely to consume the least amount of power in implementing the desired logic function.

Abstract: Existing chip select comparator logic (42) is used to compare a portion of the address value with a range of chip select addresses to provide a match signal for use by both the chip select logic (70) and a breakpoint logic circuit (50.x). The match signal is generated by the chip select logic circuit and is reused by the breakpoint logic circuit to perform a different and distinct function. By using the match signal and a breakpoint enable bit, the breakpoint logic circuit selectively asserts a breakpoint signal. Subsequently, a central processing unit (12) receives the breakpoint signal and initiates a breakpoint exception operation to determine whether the breakpoint condition is met and whether further action should be taken.

Abstract: A data processing system (10) allows an authorized user to unlock a security mode by providing a code stored in a plurality of mask registers (60,62,66) such that the system is selectively allowed to communicate with an external device. When an reset signal is received, a selector (48) selects a first mask register (60) and retrieves a first stored address value and a first stored data value therefrom. The first stored address and data values are respectively compared with a first address value and a first data value by a comparator (44). This process of selecting and comparing continues until a final match signal is asserted. When the final match signal is asserted, a secure signal is negated and the system may communicate with the external user.

Abstract: Method and apparatus in a data processing system (10) for selectively inserting bus cycle idle time. The present invention allows a data processing system (10) to selectively insert a predetermined number of idle clocks at the end of a bus cycle. In one embodiment of the present invention, there is a base register (48) and an option register (46) corresponding to each one of the chip select terminals (73). In one embodiment of the present invention, each option register (46) includes a user programmable idle control bit (110). If a first chip select is used to select a peripheral device during a bus cycle to that same peripheral device, the idle control bit (110) which corresponds to the first chip select determines whether or not one or more idle clocks will be inserted after that bus cycle.

Abstract: A pipelined data processor (10) has a control unit (14') that detects an illegal instruction as well as legal instruction opcodes. An opcode decoder (28) decodes instructions. In response to decoding an illegal instruction, opcode decoder (28) provides no output signal. In response to decoding a legal instruction, opcode decoder (28) provides one of a plurality of output signals. A ROM (27) provides a first output in response to receiving no output from the decoder (28), and provides one of a plurality of second outputs in response to receiving one of a plurality of output signals from decoder (28). The first output of the ROM (27) is a first microword of a routine for processing the illegal instruction. Each of the second outputs of the ROM (27) is a first microword of a routine for processing the legal instruction received from the decoder (28).

Abstract: Data processor (10) configures internal circuitry during execution of a reset operation in response a logic state of a Mode Select signal. If an external bus control (44) determines the Mode Select signal is in a first logic state, configuration data is provided from a mask register (40). The data is transferred to a plurality of configuration registers (50) and, subsequently, to a remaining portion of data processor (10). If the Mode Select signal is in a second logic state, configuration data is provided from a plurality of bus terminals (48). The data is transferred to the plurality of configuration registers (50). The contents of the plurality of configuration registers (50) are transferred to bus interface unit (42) which subsequently transfers the data to a remaining portion of data processor (10).

Abstract: A mask programmable register (40) determines a default configuration of a data processor during a reset operation. The default configuration is driven to a plurality of external integrated circuit pins (48) of the data processor with weak drivers (528, 534, 540, 546). Then, on an individual pin basis, an external user (11) may choose to allow each integrated circuit pin to remain in a default state or be drive with an external configuration value. When the external user chooses to allow the integrated circuit pin to remain in the default state, an internal default configuration data value provided by the internal mask programmable register is output by the integrated circuit pin. Conversely, when the external user chooses to override the default state, the user may drive the external configuration value to the integrated circuit pin using an external data source.

Abstract: An integrated circuit terminal of a data processing system (10) is used to communicate multiplexed signals with an external device. During a reset operation in which a reset signal is asserted, a desired internal clock signal is driven to the integrated circuit terminal such that an emulation system (52) may use the internal clock signal to synchronize an emulation operation. After the reset signal is negated, the emulation system synthesizes the internal clock signal for use during emulation. External visibility of a write operation to a register which controls pertinent signal parameters is provided via other integrated circuit terminals when the data processor operates in an emulation mode. The external visibility allows the development system to make similar changes to corresponding signal parameters therein. Therefore, the development system is able to accurately synchronize an emulation operation even when signal parameters are modified during operation.

Abstract: Method and apparatus for performing read accesses from a counter (40) while avoiding the large rollover error that may occur when the counter (40) is read using more than one read access cycle. In one embodiment, the present invention monitors the most significant bit of the lower portion (44) of counter (40) for a transition indicating that a rollover has taken place. If a rollover has not occurred, read accesses take place in the normal manner. However, if a rollover has occurred during the latency period between a read access from the upper portion (42) of counter (40) and a corresponding read access from the lower portion (44) of counter (40), the read access from the lower portion (44) is inhibited and a default value is placed on the bus (36) instead.

Abstract: A data processor (10) and method which provides show-cycles on a fast multiplexed bus (28) using two distinct modes of operation. A first mode of operation supports a standard show-cycle on a multiplexed bus for interface to a passive device such as a logic analyzer (100). A second mode of operation supports emulation tools (100) with real-time tracking of control functions using a multiplexed bus. During each of the modes of operation of the data processor (10), both read and write show cycles are supported and are consistently provided in a similar format.

Abstract: Method and apparatus for performing multiplexed and non-multiplexed bus cycles in a data processing system (10). The present invention allows a data processing system (10) to switch from multiplexed bus cycles to non-multiplexed bus cycles, and vice-versa, without requiring the data processing system (10) to be reset. In one embodiment of the present invention, a single user programmable control bit (90) is used to select whether an external bus cycle will be multiplexed or non-multiplexed. In more complex embodiments of the present invention, the ability to switch between multiplexed external bus cycles and non-multiplexed external bus cycles may be achieved by way of a plurality of user programmable register fields (96, 100, 102, and 104) located in registers 44. The plurality of user programmable register fields (96, 100, 102, and 104) may be associated with one or more chip select signals.

Abstract: A method and apparatus for scan testing an array (20) in a data processing system (10). In one form, the present invention uses a scanning sense amplifier (22x) which can perform the three functions of a sense amplifier, a master test latch for scan testing, and a slave test latch for scan testing. Using one scanning sense amplifier (22x) to perform all three functions reduces the amount of circuitry required to scan test an array (20). The same stimulus is applied twice to the array (20); and half of the output data bits are scanned out during each application of the stimulus. One extra output data bit is also scanned out during each application of the stimulus. The end result is a reduction in the circuitry required to perform scan testing.

Abstract: An interrupt mechanism allows an interrupt request signal to be adjusted to any priority level specified by the user and provides to a CPU an encoded interrupt signal which either indicates that the interrupt priority has been adjusted or identifies a highest prioritized interrupt request when no adjustment in priority is made. A first logic circuit functions to receive a priority adjust request signal and compares the adjust signal with one or more interrupt signals to determine if an adjustment is required. A second logic circuit functions to identify the highest prioritized interrupt request of a plurality of interrupt requests and provides the encoded interrupt signal in response thereto. In one form, the encoded interrupt signal is translated into a value for use in a software exception processing routine within the CPU. The software exception processing routine can perform a variety of user specified functions with the encoded adjusted priority interrupt signal.