Abstract: The method and system supports multiple bandwidth traffic over a single CPRI (common public radio interface) link (109) using a single bandwidth DMA (direct memory access) engine (505) and fast Fourier transform/inverse fast Fourier transform processing. (402, 404) The invention exploits fast Fourier transform/inverse fast Fourier transform properties and is particularly suitable for supporting LTE (Long Term Evolution) cellular communication systems (100) The CPRI Media Access Control is configured in each CPRI lane to run at the maximum bandwidth among the bandwidths required. In the uplink, lower bandwidth data samples are padded with zeros and flexible positioning may be used to arrange the data in a CPRI frame. In the downlink, the radio equipment receiver (106) only processes the relevant data and ignores any interpolated samples. The invention is compatible with CPRI and LTE standards.

Abstract: The method and system supports multiple bandwidth traffic over a single CPRI (common public radio interface) link (109) using a single bandwidth DMA (direct memory access) engine (505) and fast Fourier transform/inverse fast Fourier transform processing. (402, 404) The invention exploits fast Fourier transform/inverse fast Fourier transform properties and is particularly suitable for supporting LTE (Long Term Evolution) cellular communication systems (100) The CPRI Media Access Control is configured in each CPRI lane to run at the maximum bandwidth among the bandwidths required. In the uplink, lower bandwidth data samples are padded with zeros and flexible positioning may be used to arrange the data in a CPRI frame. In the downlink, the radio equipment receiver (106) only processes the relevant data and ignores any interpolated samples. The invention is compatible with CPRI and LTE standards.

Abstract: A device includes a first memory unit adapted to store encrypted instructions, a processor adapted to execute decrypted instructions, a second memory unit accessible by the processor, and a decryption unit. The device includes a key database and a key selection circuit, wherein the key selection circuit is adapted to select a selected decryption key from the key database for decrypting encrypted instructions. The selection is responsive to a fixed selection information stored within the integrated circuit and to received key selection information. A method includes a stage of receiving encrypted instructions; and executing decrypted instructions by a processor. The method includes receiving key selection information, selecting a selected decryption key out of a key database in response to fixed selection information and to the received key selection information, and decrypting encrypted instructions using the selected decryption key.

Abstract: A device and a method for fetching instructions. The device includes a processor adapted to execute instructions; a high level memory unit adapted to store instructions; a direct memory access (DMA) controller that is controlled by the processor; an instruction cache that includes a first input port and a second input port; wherein the instruction cache is adapted to provide instructions to the processor in response to read requests that are generated by the processor and received via the first input port; wherein the instruction cache is further adapted to fetch instructions from a high level memory unit in response to read requests, generated by the DMA controller and received via the second input port.

Abstract: A device that includes multiple processors that are connected to multiple level-one cache units. The device also includes a multi-port high-level cache unit that includes a first modular interconnect, a second modular interconnect, multiple high-level cache paths; whereas the multiple high-level cache paths comprise multiple concurrently accessible interleaved high-level cache units. Conveniently, the device also includes at least one non-cacheable path. A method for retrieving information from a cache that includes: concurrently receiving, by a first modular interconnect of a multiple-port high-level cache unit, requests to retrieve information. The method is characterized by providing information from at least two paths out of multiple high-level cache paths if at least two high-level cache hit occurs, and providing information via a second modular interconnect if a high-level cache miss occurs.

Abstract: A method for fast tracking and jitter improvement in an asynchronous sample rate conversion includes a digital phase locked loop (DPLL) for an asynchronous sample rate conversion (ASRC) device. A control apparatus in the DPLL includes a gain controller that sets and maintains gains (Ki, Kp) of two branches of the control apparatus at a fixed value, which enables searching of a desired value by the DPLL to determine a neighborhood of the desired value, and reduces the gains when the number of samples reaches a predetermined number. Processing units in the DPLL generate and process first and second input signals based on an input clock, an output clock, and a system clock. The second input signal is processed using two branches. Signals resulting from the two branches are re-aligned according to a changed status of the first processed input signal such that the signals resulting from the two branches are sampled in the same input clock interval.

Abstract: A device and a method for providing core redundancy, the device includes: multiple cores; a core operability unit adapted to indicate an operability of each core out of the multiple cores; and a core control signal unit adapted to provide mapping signals that comprise virtual core to physical core mapping signals and physical core to virtual core mapping signals; wherein each core out of the multiple cores comprises at least one interrupt interface, and a crossbar interface which are responsive to at least one mapping signal.

Abstract: A method for fast tracking and jitter improvement in an asynchronous sample rate conversion includes a digital phase locked loop (DPLL) for an asynchronous sample rate conversion (ASRC) device. A control apparatus in the DPLL includes a gain controller that sets and maintains gains (Ki, Kp) of two branches of the control apparatus at a fixed value, which enables searching of a desired value by the DPLL to determine a neighborhood of the desired value, and reduces the gains when the number of samples reaches a predetermined number. Processing units in the DPLL generate and process first and second input signals based on an input clock, an output clock, and a system clock. The second input signal is processed using two branches. Signals resulting from the two branches are re-aligned according to a changed status of the first processed input signal such that the signals resulting from the two branches are sampled in the same input clock interval.

Abstract: A device and a method for fetching instructions. The device includes a processor adapted to execute instructions; a high level memory unit adapted to store instructions; a direct memory access (DMA) controller that is controlled by the processor; an instruction cache that includes a first input port and a second input port; wherein the instruction cache is adapted to provide instructions to the processor in response to read requests that are generated by the processor and received via the first input port; wherein the instruction cache is further adapted to fetch instructions from a high level memory unit in response to read requests, generated by the DMA controller and received via the second input port.

Abstract: A device that includes a first memory unit adapted to store encrypted instructions, a processor adapted to execute decrypted instructions, a second memory unit accessible by the processor, and a decryption unit. The device is characterized by including a key database and a key selection circuit, wherein the key selection circuit is adapted to select a selected decryption key from the key database for decrypting encrypted instructions. The selection is responsive to a fixed selection information stored within the integrated circuit and to received key selection information. A method that includes a stage of receiving encrypted instructions; and executing decrypted instructions by a processor. The method is characterized by receiving key selection information, selecting a selected decryption key out of a key database in response to fixed selection information and to the received key selection information, and decrypting encrypted instructions using the selected decryption key.

Abstract: A device that includes multiple processors that are connected to multiple level-one cache units. The device also includes a multi-port high-level cache unit that includes a first modular interconnect, a second modular interconnect, multiple high-level cache paths; whereas the multiple high-level cache paths comprise multiple concurrently accessible interleaved high-level cache units. Conveniently, the device also includes at least one non-cacheable path. A method for retrieving information from a cache that includes: concurrently receiving, by a first modular interconnect of a multiple-port high-level cache unit, requests to retrieve information. The method is characterized by providing information from at least two paths out of multiple high-level cache paths if at least two high-level cache hit occurs, and providing information via a second modular interconnect if a high-level cache miss occurs.

Abstract: An adaptive proportional integral control loop determines a ratio of the input sampling rate to the output sampling rate for use in asynchronous sample rate conversion. An input counter counts input samples and its output is sampled at the output sampling rate by a latch. The output of the latch is passed through a closed loop circuit comprising variable gain and integrator sections.

Abstract: An adaptive proportional integral control loop (209, 210) provides an accurate measurement of input to output sampling rates for use in asynchronous sampling rate conversion. An input counter (200) counts inputs samples and its output is sampled at the output sampling rate by a latch (201). The output of the latch (201) is passed through a closed loop circuit (210) comprising variable gain (203, 205) and integrator (208) sections. The output of the integrator can be used to steer the co-efficients of a polyphase filter. The invention has the advantages of a fast settling time and good quantisation noise attenuation.