Abstract: A video imaging system includes a digital image sensor for performing image capture operations and a digital image processor for performing image processing operations. The digital image sensor includes a sensor array outputting digital pixel data, an image buffer for storing the pixel data, a first processor and a first interface circuit for transferring the pixel data onto a pixel bus. The digital image processor includes a second interface circuit coupled to receive the pixel data from the pixel bus, a frame buffer coupled to store the pixel data, an image processing pipeline for processing the pixel data stored in the frame buffer into video data, and a second processor. The digital image sensor and the digital image processor transfer control information over a control interface bus and the digital image sensor performs the image capture operations independent of the image processing operations performed by the digital image processor.

Abstract: A system-on-chip imaging system includes an image sensor of a two-dimensional array of pixel elements providing pixel data representing an image of a scene, a data memory for storing pixel codewords whereby at least some of the pixel codewords are indicative of the pixel data, a programmable lookup table for providing LUT codewords as output data, and a processing unit for receiving LUT codewords from the lookup table and generating output image data. In operation, a first pixel codeword stored in the data memory is used to index the lookup table for causing the lookup table to provide a respective LUT codeword to the processing unit. The processing unit operates to perform one or more image processing functions in response to the LUT codeword. The lookup table can be programmed to perform a variety of image processing functions, including defective pixel correction, CDS subtraction, privacy masking and dark signal subtraction.

Abstract: An image sensor includes a sensor or a pixel array, a data memory, and a logic circuit, all fabricated on the same integrated chip. The sensor or pixel array outputs digital signals as pixel data representing an image of a scene. The data memory is coupled to the sensor or pixel array for storing the pixel data. The logic circuit is coupled to the data memory and provides a memory interface for exporting the pixel data. The memory interface can be one of a SRAM, a DRAM or a packet protocol synchronous DRAM interface. Including a memory interface in the image sensor allows the image sensor to be coupled directly to the memory interface port of an external image processing unit. The image processing unit can access the image sensor using conventional memory access protocols, thus improving the efficiency and reducing the operational complexity of the image processing unit.

Abstract: An image sensor includes a sensor array, a data memory for storing pixel data and a pixel normalization circuit. The sensor array has a two-dimensional array of pixel elements and outputs digital signals as pixel data representing an image of a scene. The pixel data outputted by the sensor array are arranged in a sensor-bit arrangement and the pixel normalization circuit rearranges the pixel data into a pixel-bit order. In another embodiment, an image sensor includes a sensor array, a data memory, and a pixel normalization circuit, all fabricated on a single integrated circuit. The pixel normalization circuit includes one or more of a pixel rearrangement circuit, a Gray code to binary conversion circuit, a reset subtract circuit, and a multiple sampling normalization circuit. Finally, a Gray code to binary conversion circuit is provided for high speed conversion.

Abstract: An image sensor includes a sensor array, a data memory for storing pixel data and a pixel normalization circuit. The sensor array has a two-dimensional array of pixel elements and outputs digital signals as pixel data representing an image of a scene. The pixel data outputted by the sensor array are arranged in a sensor-bit arrangement and the pixel normalization circuit rearranges the pixel data into a pixel-bit order. In another embodiment, an image sensor includes a sensor array, a data memory, and a pixel normalization circuit, all fabricated on a single integrated circuit. The pixel normalization circuit includes one or more of a pixel rearrangement circuit, a Gray code to binary conversion circuit, a reset subtract circuit, and a multiple sampling normalization circuit. Finally, a Gray code to binary conversion circuit is provided for high speed conversion.

Abstract: An image sensor, including a substrate having formed thereon by a CMOS process a digital sensor array having a plurality of digital pixel sensors which output analog signals corresponding to a desired image. The digital sensor array further includes supporting circuitry for converting the analog signals produced by the digital pixel sensors to digital signals corresponding to the desired image. Filter circuitry, for converting the digital signals to digital values representative of the light intensity impinging upon the plurality of digital pixel sensors, is also formed on the substrate using CMOS fabrication processes. Memory devices, including a data memory, a threshold memory, and a time index memory are formed on the substrate using CMOS fabrication techniques. A clock circuit is also formed on the substrate using CMOS fabrication processes. Programmable logic structures are formed on the substrate using CMOS fabrication processes.

Abstract: A method of optimizing the exposure times of regions of pixels of an image sensor array during exposure is accomplished by utilizing time interval sampling of an image sensor array comprising of pixels configured to generate digital image signals. Luminance values are extracted from each digital image signal and analyzed to determine if a pixel has reached the optimal exposure. If a pixel has reached the optimal exposure, subsequent digital image signals from this pixel will not be recorded. This preserves the recording of the optimal digital image signal generated by the pixel at the time when the pixel reached its optimal exposure. This process of selectively terminating the recording of digital image signals based on optimal exposures of the pixels can be performed on individual pixels or can be performed on a region of pixels.

Abstract: An image sensor includes a sensor or a pixel array, a data memory, and a logic circuit, all fabricated on the same integrated chip. The sensor or pixel array outputs digital signals as pixel data representing an image of a scene. The data memory is coupled to the sensor or pixel array for storing the pixel data. The logic circuit is coupled to the data memory and provides a memory interface for exporting the pixel data. The memory interface can be one of a SRAM, a DRAM or a packet protocol synchronous DRAM interface. Including a memory interface in the image sensor allows the image sensor to be coupled directly to the memory interface port of an external image processing unit. The image processing unit can access the image sensor using conventional memory access protocols, thus improving the efficiency and reducing the operational complexity of the image processing unit.