Abstract: An integrated circuit includes a first transceiver of multiple simultaneous bidirectional (SBD) transceivers that is coupled to a second transceiver across a channel. A signal detection circuit is coupled to a first receiver, a first transmitter, and to an I/O pad of the first transceiver. The signal detection circuit deactivates the first receiver. The signal detection circuit activates an activation circuit in response to deactivating the first receiver. The signal detection circuit detects, using the activation circuit, whether the second transmitter enters a transmission mode based on a transmission status of the first transmitter and on voltage transitions detected over the I/O pad from the second transmitter.

Abstract: A system includes first transceivers coupled to data lanes, which are coupled to second transceivers and a first encoder coupled to the first transceivers. The first encoder, responsive to detecting a transmission signal to begin a transmission mode, determines that first bits to be transmitted by the first transceivers over the data lanes include over fifty percent of a first binary value. The first encoder generates a first data-bus-inversion (DBI) polarity signal that alternates in polarity and generates first DBI-encoded bits of the first of bits based on the first DBI polarity signal. The first encoder causes the transmission signal to be transmitted to a second encoder coupled to the second transceivers, the transmission signal to synchronize DBI encoding between the first and second encoders.

Abstract: An integrated circuit includes a plurality of thermal sensors integrated within digital domain circuitry and powered by a digital supply voltage. An activation register receives activation data from a tester unit. Control logic, in response to the activation register being written with the activation data, enters a thermal calibration mode, deactivates a plurality of digital logic units of the digital domain circuitry, and causes a reference clock received from the tester to drive the plurality of the thermal sensors.

Abstract: A system includes a transmission driver coupled to a channel, a capacitor coupled in series to the channel, and a receiver coupled to the channel. The receiver includes a front-end circuit to detect, as data, transitions in voltage over the channel, the front-end circuit including an activation switch. A voltage swing detector is coupled between the channel and the activation switch. The voltage swing detector detects a voltage swing in the voltage that satisfies one of a first threshold value or a second threshold value and causes, in response to the detection, the activation switch to one of open or close, respectively.

Abstract: A receiver includes a multi-phase clock generator to generate phases of a clock signal and a global phase interpolator (PI) circuit coupled to the multi-phase clock generator and to clock and data recovery (CDR) circuitry. The global PI circuit generates initial-adjusted phases from the phases of the clock signal based on a control signal received from the CDR circuitry. A first local PI receives the initial-adjusted phases of the clock signal and applies a first fixed phase shift to the initial-adjusted phases to generate first final-adjusted phases of the clock signal that are useable to sample a first level of multiple levels of a pulse-amplitude-modulated (PAM) data stream.

Abstract: Technologies directed to determine whether a frequency of a clock signal is outside a specified frequency range are described. One integrated circuit includes a signal generator circuit, a voltage divider circuit, and digital logic circuitry. The signal generator circuit generates phase signals from a clock signal. The voltage divider circuit converts a frequency of the clock signal to a voltage representing the frequency. The voltage divider circuit includes a first resistor and a first switched-capacitor structure to receive the phase signals. An average resistance of the first switched-capacitor structure is inversely proportional to the frequency of the clock signal. The digital logic circuitry can determine, using the voltage, whether the frequency is outside of a specified frequency range, and output an indication responsive to the frequency being outside the specified frequency range.

Abstract: A system includes a series of first/second transceivers mutually coupled over data lanes as bidirectional transceivers, and first/second control logic coupled to the first/second transceivers, respectively. An encoding of bit inversions by the first/second control logic causes: first pair of transceivers coupled over a first data lane to transmit non-inverted bits in a first direction and a second direction over the first data lane; second pair of transceivers coupled over a second data lane to transmit inverted bits in a first direction but not a second direction over the second data lane; third pair of transceivers coupled over a third data lane to transmit inverted bits in the second direction but not the first direction over the third data lane; and fourth pair of transceivers coupled over a fourth data lane to transmit inverted bits in the first direction and the second direction over the fourth data lane.

Abstract: A receiver includes a multi-phase clock generator to generate phases of a clock signal and a global phase interpolator (PI) circuit coupled to the multi-phase clock generator and to clock and data recovery (CDR) circuitry. The global PI circuit generates initial-adjusted phases from the phases of the clock signal based on a control signal received from the CDR circuitry. A first local PI receives the initial-adjusted phases of the clock signal and applies a first fixed phase shift to the initial-adjusted phases to generate first final-adjusted phases of the clock signal that are useable to sample a first level of multiple levels of a pulse-amplitude-modulated (PAM) data stream.

Abstract: Technologies directed to determine whether a frequency of a clock signal is outside a specified frequency range are described. One integrated circuit includes a signal generator circuit, a voltage divider circuit, and digital logic circuitry. The signal generator circuit generates phase signals from a clock signal. The voltage divider circuit converts a frequency of the clock signal to a voltage representing the frequency. The voltage divider circuit includes a first resistor and a first switched-capacitor structure to receive the phase signals. An average resistance of the first switched-capacitor structure is inversely proportional to the frequency of the clock signal. The digital logic circuitry can determine, using the voltage, whether the frequency is outside of a specified frequency range, and output an indication responsive to the frequency being outside the specified frequency range.

Abstract: An integrated circuit includes a bandgap reference circuit configured to generate, from a digital chip supply voltage, a reference voltage and a proportional-to-absolute temperature (PTAT) voltage. A voltage-to-frequency (VTF) readout circuit to receive the reference voltage and the PTAT voltage as inputs. The VTF readout circuit includes sets of switched capacitors that operate as a voltage divider. The capacitors of the sets of switched capacitors are selectively charged by the PTAT voltage and generate a feedback voltage. A voltage-controlled oscillator (VCO) is driven by a difference between the feedback voltage and the reference voltage and generates a VCO clock. A clock generator generates a feedback clock based on the VCO clock. First switches of the sets of switched capacitors are controlled by the feedback clock.