Abstract: A method, apparatus and product includes obtaining a logical representation of a quantum circuit and selecting a quantity of physical qubits for a physical representation of the quantum circuit, wherein the selecting of the quantity is based on a utility per-qubit metric that is used to define a utility per-qubit score of the quantum circuit. The utility per-qubit score is determined based on a ratio between a quality score of the quantum circuit when using the quantity of physical qubits and between a cost function of the quantum circuit, wherein the quality score is defined by a quality metric that is monotonically correlated to error rates of logical output qubits. The quantum circuit is synthesized using the quantity of the physical qubits that was selected.

Abstract: Method, apparatus and product for modeling of quantum circuits and usages thereof. A method comprises obtaining a model of a quantum circuit that comprises a set of decision variables, corresponding domains, and constraints, wherein the set of decision variables comprise gate assignment decision variables that define an assignment of a gate to a qubit in a cycle in the quantum circuit. The method comprises automatically determining a set of valuations for the set of decision variables. The set of valuations are selected from the corresponding domains and satisfy the constraints. Based on the set of valuations the quantum circuit is synthesized.

Abstract: A method, system and product comprising: obtaining a directed acyclic graph representing a quantum circuit, the directed acyclic graph comprising a set of blocks and connections therebetween, wherein a connection between a first block and a second block indicates passing an output value of a qubit outputted by the first block to be an input value of a qubit manipulated by the second block; determining a Constraint Satisfaction Problem (CSP) based on the directed acyclic graph, wherein the CSP comprises one or more constraints based on the connections defined by the directed acyclic graph; automatically solving the CSP, wherein said automatically solving comprises selecting an implementation to each block that adheres to the one or more constraints; and synthesizing a gate-level representation of the quantum circuit based on the solution to the CSP.

Abstract: A method, system and product relating to quantum computing. The method comprises using a quantum computer to execute a quantum program a plurality of times, wherein during each execution of the quantum program: reaching an intermediate state, wherein the intermediate state is obtained prior to reaching the terminating cycle of the quantum program; and performing a measurement of a qubit at the intermediate state, whereby obtaining a plurality of measurements of the qubit at the intermediate state in a plurality of executions of the quantum program. The method further comprises determining a value of the qubit at the intermediate state based on the plurality of measurements obtained of the qubit at the intermediate state.

Abstract: Method, apparatus and product for modeling of quantum circuits and usages thereof. A method includes obtaining a model of a quantum circuit that comprises a set of decision variables, corresponding domains, and constraints, wherein the set of decision variables comprise gate assignment decision variables that define an assignment of a gate to a qubit in a cycle in the quantum circuit. The method includes automatically determining a set of valuations for the set of decision variables. The set of valuations are selected from the corresponding domains and satisfy the constraints. Based on the set of valuations the quantum circuit is synthesized.

Abstract: A method, system and product comprising: obtaining a functional-level representation of a quantum circuit that comprises a functional block; synthesizing a gate-level representation of the quantum circuit based on the functional-level representation of the quantum circuit, wherein the gate-level representation of the quantum circuit comprises a first sub-circuit and a second sub-circuit; providing the gate-level representation to a gate-level processing component; obtaining, from the gate-level processing component, a change indication indicating that the gate-level processing component modified the first sub-circuit, whereby determining a modified first sub-circuit; in response to the change indication, synthesizing a modified second sub-circuit based on a knowledge of an existence of the modified first sub-circuit.