Patents by Inventor Ofer Bokobza

Ofer Bokobza has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Design-based method for grouping systematic defects in lithography pattern writing system
    Patent number: 7760347
    Abstract: Methods and apparatus for categorizing defects on workpieces, such as semiconductor wafers and masks used in lithographically writing patterns into such wafers are provided. For some embodiments, by analyzing the layout in the neighborhood of the defect, and matching it to similar defected neighborhoods in different locations across the die, defects may be categorized by common structures in which they occur.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: July 20, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Youval Nehmadi, Ofer Bokobza, Ariel Ben-Porath, Erez Ravid, Rinat Shishi, Vicky Svidenko, Gilad Almogy, Jacob J. Orbon, Jr.
  • Grouping systematic defects with feedback from electrical inspection
    Patent number: 7760929
    Abstract: Methods and apparatus for categorizing defects on workpieces, such as semiconductor wafers and masks used in lithographically writing patterns into such wafers are provided. For some embodiments, by analyzing the layout in the neighborhood of the defect, and matching it to similar defected neighborhoods in different locations across the die, defects may be categorized by common structures in which they occur.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: July 20, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Jacob J. Orbon, Youval Nehmadi, Ofer Bokobza, Ariel Ben-Porath, Erez Ravid, Rinat Shimshi, Vicky Svidenko
  • DESIGN-BASED MONITORING
    Publication number: 20090007030
    Abstract: A method for monitoring fabrication of an integrated circuit (IC) on a semiconductor wafer includes generating a product design profile (PDP) using an electronic design automation (EDA) tool, the PDP comprising an indication of a site in a layer of the IC that is susceptible to a process fault. Upon fabricating the layer of the IC on the wafer, a process monitoring tool is applied to perform a measurement at the site in the layer responsively to the PDP.
    Type: Application
    Filed: October 3, 2006
    Publication date: January 1, 2009
    Inventors: Youval Nehmadi, Josephine Phua, Jacob Joseph Orbon, JR., Ariel Ben-Porath, Evgeny Levin, Ofer Bokobza
  • GROUPING SYSTEMATIC DEFECTS WITH FEEDBACK FROM ELECTRICAL INSPECTION
    Publication number: 20070052963
    Abstract: Methods and apparatus for categorizing defects on workpieces, such as semiconductor wafers and masks used in lithographically writing patterns into such wafers are provided. For some embodiments, by analyzing the layout in the neighborhood of the defect, and matching it to similar defected neighborhoods in different locations across the die, defects may be categorized by common structures in which they occur.
    Type: Application
    Filed: October 27, 2006
    Publication date: March 8, 2007
    Inventors: JACOB ORBON, Youval Nehmadi, Ofer Bokobza, Ariel Ben-Porath, Erez Ravid, Rinat Shimshi, Vicky Svidenko
  • DESIGN-BASED METHOD FOR GROUPING SYSTEMATIC DEFECTS IN LITHOGRAPHY PATTERN WRITING SYSTEM
    Publication number: 20060269120
    Abstract: Methods and apparatus for categorizing defects on workpieces, such as semiconductor wafers and masks used in lithographically writing patterns into such wafers are provided. For some embodiments, by analyzing the layout in the neighborhood of the defect, and matching it to similar defected neighborhoods in different locations across the die, defects may be categorized by common structures in which they occur.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 30, 2006
    Inventors: YOUVAL NEHMADI, Ofer Bokobza, Ariel Ben-Porath, Erez Ravid, Rinat Shimsht, Vicky Svidenko, Gilad Almogy
  • Design-based monitoring
    Patent number: 7135344
    Abstract: A method for monitoring fabrication of an integrated circuit (IC) on a semiconductor wafer includes generating a product design profile (PDP) using an electronic design automation (EDA) tool, the PDP comprising an indication of a site in at least one layer of the IC that is susceptible to a process fault. Upon fabricating at least one layer of the IC on the wafer, a process monitoring tool is applied to perform a measurement at the site in at least one layer responsively to the PDP.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: November 14, 2006
    Assignee: Applied Materials, Israel, Ltd.
    Inventors: Youval Nehmadi, Josephine Phua, Jacob Joseph Orbon, Jr., Ariel Ben-Porath, Evgeny Levin, Ofer Bokobza
  • Design-based monitoring
    Publication number: 20050010890
    Abstract: A method for monitoring fabrication of an integrated circuit (IC) on a semiconductor wafer includes generating a product design profile (PDP) using an electronic design automation (EDA) tool, the PDP comprising an indication of a site in at least one layer of the IC that is susceptible to a process fault. Upon fabricating at least one layer of the IC on the wafer, a process monitoring tool is applied to perform a measurement at the site in at least one layer responsively to the PDP.
    Type: Application
    Filed: February 17, 2004
    Publication date: January 13, 2005
    Inventors: Youval Nehmadi, Josephine Phua, Jacob Orbon, Ariel Ben-Porath, Evgeny Levin, Ofer Bokobza