Abstract: A device having a plurality of thin film photovoltaic cells (PV) formed over a passivation layer. The device comprises a plurality of thin film photovoltaic (PV) cells formed over the passivation layer, each PV cell includes at least a lower conducting layer (LCL) and an upper conducting layer (UCL); and a conducting path connecting at least a UCL of a first PV cell to at least a LCL of a second PV cell, wherein at least a first array of PV cells comprised of at least a first portion of the plurality of PV cells is connected by the respective UCL and LCL of each PV cell to provide a first voltage output. In an embodiment the passivation layer is formed over a target integrated circuit (TIC), the TIC having a top surface and a bottom surface.

Abstract: A device having a plurality of thin film photovoltaic cells (PV) formed over a passivation layer. The device comprises a plurality of thin film photovoltaic (PV) cells formed over the passivation layer, each PV cell includes at least a lower conducting layer (LCL) and an upper conducting layer (UCL); and a conducting path connecting at least a UCL of a first PV cell to at least a LCL of a second PV cell, wherein at least a first array of PV cells comprised of at least a first portion of the plurality of PV cells is connected by the respective UCL and LCL of each PV cell to provide a first voltage output. In an embodiment the passivation layer is formed over a target integrated circuit (TIC), the TIC having a top surface and a bottom surface.

Abstract: A system and method for fabricating a self-powering integrated circuit chip having an integrated circuit, which may be a MEMS or CMOS device or the like and a thin film photovoltaic cell stack overlayed thereupon or on the opposite side of the substrate on which the IC is manufactured upon.

Abstract: A target integrated circuit (TIC) having a top conductive layer (TCL) that may be connected to a plurality of cells that are further integrated over the TIC. Each of the plurality of cells comprises two conductive layers, a lower conductive layer (LCL) below the cell and an upper conductive layer (UCL) above the cell. Both conductive layers may connect to the TCL of the TIC to form a super IC structure combined of the TIC and the plurality of cells connected thereto. Accordingly, conductivity between the TIC as well as auxiliary circuitry to the TIC maybe achieved.

Abstract: An integrated circuit (IC) combination of a target integrated circuit (TIC) and a plurality of thin film photovoltaic cells (PV) connected thereto. The IC comprises a target integrated circuit (TIC) having a top surface and a bottom surface; a plurality of thin film photovoltaic (PV) cells formed over at least one of the top surface and the bottom surface of the TIC, each PV cell includes at least a lower conducting layer (LCL) and an upper conducting layer (UCL); and a conducting path connecting at least a UCL of a first PV cell to at least a LCL of a second PV cell, wherein at least a first array of PV cells comprised of at least a first portion of the plurality of PV cells is connected by the respective UCL and LCL of each PV cell to provide a first voltage output.

Abstract: An integrated circuit (IC) combination of a target integrated circuit (TIC) and a plurality of thin film photovoltaic cells (PV) connected thereto. The IC comprises a target integrated circuit (TIC) having a top surface and a bottom surface; a plurality of thin film photovoltaic (PV) cells formed over at least one of the top surface and the bottom surface of the TIC, each PV cell includes at least a lower conducting layer (LCL) and an upper conducting layer (UCL); and a conducting path connecting at least a UCL of a first PV cell to at least a LCL of a second PV cell, wherein at least a first array of PV cells comprised of at least a first portion of the plurality of PV cells is connected by the respective UCL and LCL of each PV cell to provide a first voltage output.

Abstract: A target integrated circuit (TIC) having a top conductive layer (TCL) that may be connected to a plurality of cells that are further integrated over the TIC. Each of the plurality of cells comprises two conductive layers, a lower conductive layer (LCL) below the cell and an upper conductive layer (UCL) above the cell. Both conductive layers may connect to the TCL of the TIC to form a super IC structure combined of the TIC and the plurality of cells connected thereto. Accordingly, conductivity between the TIC as well as auxiliary circuitry to the TIC maybe achieved.

Abstract: A system and method for fabricating a self-powering integrated circuit chip having an integrated circuit, which may be a MEMS or CMOS device or the like and a thin film photovoltaic cell stack overlayed thereupon or on the opposite side of the substrate on which the IC is manufactured upon.