Abstract: A cladded wall system for constructing cladded cast-in-place concrete walls that are each integrated with lost forms comprising a self-supporting structure made of a plurality of prefabricated cladded panels (PCPs) constituting an exterior lost form, at least one architectural element constituting an interior lost form, and a plurality of concrete integratable connecting units by which each of said PCPs is connected to said interior lost form.

Abstract: A data transfer retry method includes: A. receiving a particular atomic data transfer command from a director; B. processing identification information associated with the particular atomic data transfer command; C. comparing the identification information associated with the particular atomic data transfer command to identification information of a previous atomic data transfer command received from the director; D. determining that the particular atomic data transfer command is a retry command of the previous atomic data transfer command received from the director; E. determining a status of the execution of the previous atomic data transfer command received from the director; and F. processing the particular atomic data transfer command based on the status of the execution of the previous atomic data transfer command determined in Step E.

Abstract: An error checking system includes an input device for receiving a data element including parity information; a parity check device for checking the parity information of the data element to determine whether the data element is valid; a CRC generator coupled to the parity check device for generating a CRC for the data element; and an output device for transmitting the data element with the parity information and CRC to a downstream device over a transmission link. The parity check device is operative to output a corruption signal to the CRC generator if the parity check device determines that the data element is invalid, to instruct the CRC generator to corrupt the CRC generation for that data element.

Abstract: A memory system having a plurality of sets of memory modules. The system includes a plurality of sets of memory controllers, each one of the memory controllers being coupled to a corresponding one of the plurality of sets of memory modules. The system includes a port for providing address and read/write control signals to the memory system. The memory controllers are interconnected in a daisy chain arrangement to the port.

Abstract: In its simplest from, the hidden rain gutter of the present invention consists of a trough having a closed cross-sectional contour that is enclosed for the most of its periphery, having an opening in its upper section adjacent to the drain opening in the roof surface layer through which rainwater is introduced into the trough. The hidden rain gutter of the present invention is configured with at least one drainage outlet and at least one distal end spaced apart from the drainage outlet. The hidden rain gutter element defines a drainage vector between the distal end and the drainage outlet In one preferred deployment of the hidden rain gutter of the present invention the drainage vector is parallel to the plane of the roof surface layer with the distal end deployed higher on the slope of the roof than the drainage outlet such that rainwater falling into the rain gutter element is directed toward the drainage outlet.

Abstract: A transmitter board transmits a copy of signals in a system being analyzed by the system analyzer. The copy of such signals comprises serial data in a low byte serial link and in a high byte serial link. The signals include special characters interspersed in a pattern with the data in the low and high byte serial links. An analyzer board includes a serializer-deserializer for receiving the transmitted serial data when the analyzer board is plugged into the transmitter board for converting the received data and the interspersed special characters in both the low and high byte serial links into corresponding data and interspersed special characters in low byte and high byte parallel links. A mismatch between the data and the interspersed pattern of special characters in the converted low byte parallel link and the pattern of special characters in the converted high byte parallel links resets the serializer-deserializer.

Abstract: A system having memory modules for storing nibbles of a word. The nibbles include an error correction/detection code. A memory controller is response to clock pulses to produce a read command. A synchronizer is responsive to the read nibbles and an associated read strobe signal for synchronizing the read nibbles and the read strobes to the clock pulses. A detection section is responsive to the clock pulses and the read command for producing a time window representative of a time duration during which each of the read strobes is expected. The detection system is responsive to each one of the read strobes and the produced time window for producing, for each one of the read strobes, a corresponding one of a plurality of NIBBLE ERROR signals. Each one of the NIBBLE ERROR signals indicates whether the corresponding one of the read strobes is within the produced window or is absent from such window.

Abstract: A system having a plurality of printed circuit broads each one having an electrical component thereon. A backplane carries a signal indicative of a performance characteristic of the electrical components on the plurality of printed circuit boards plugged into such backplane. The performance characteristic may be, for example component speed, operating protocol, etc. System start-up is interrupted upon detection of such incompatibility. After start up, upon plugging an additional printed circuit broad having an electrical component thereon with an operating incompatible with the electrical components on the plurality of printed circuit boards into the backplane, the electrical component on such additional printed circuit will not be electrically coupled to the electrical component on the additional printed circuit board from the electrical components of the plurality of printed circuit boards.

Abstract: A test system and method for testing a serializer/de-serializer system. The system includes a pair of serializer/de-serializers each having a serial data receive port and a serial data transmit port. The serializer/de-serializers are adapted to be placed in a loop-back mode in response to a loop-back signal to pass data fed to the serial data receive port to the serial data transmit port. A backplane connects the serial data transmit port of one serializer/de-serializer to the serial data receive port of a second one of the serializer/de-serializers. A tester passes data to the first serial data receive port and receives data from the data transmit port of the second one of the serializer/de-serializers with both serializer/de-serializes placed in the loop-back mode.

Abstract: A system interface having a cache memory and a plurality of directors. Each one of the plurality of directors includes a data pipe coupled between an input of such one of the directors. The data pipe includes a data pipe memory and a data pipe memory controller for controlling the data pipe memory. Each one of the directors includes microprocessor coupled to the data pipe memory controller. The system includes a switching network coupled to the cache memory to transfer data between the memory and: (a) the input of a selected one of the plurality of directors through the data pipe memory; (b) the microprocessor and the data pipe memory through the data pipe memory controller of a selected one of the plurality of directors; and (c) the microprocessor and the data pipe memory controller while by-passing the data pipe memory of a selected one of the plurality of directors.

Abstract: A memory system includes a bank of memory, an interface to a packet switching network, and a memory controller. The memory system is adapted to receive by the interface a packet based command to access the bank of memory. The memory controller is adapted to execute initialization and configuration cycles for the bank of memory. An embedded central processing unit (CPU) is included in the memory controller and is adapted to execute computer executable instructions. The memory controller is adapted to process the packet based command.

Abstract: A memory system having a plurality of sets of memory modules. The system includes a plurality of sets of memory controllers, each one of the memory controllers being coupled to a corresponding one of the plurality of sets of memory modules. The system includes a port for providing address and read/write control signals to the memory system. The memory controllers are interconnected in a daisy chain arrangement to the port.

Abstract: An innovative roofing tile is presented, the roofing tile configured to allow liquid such as rain to flow through the roofing tile. The innovative roofing tile allows the design of a roof with ahidden gutters. Such a roof is both esthetic and allows for a low-maintenance and robust gutter system.

Abstract: A system and method are provided for transferring data appended with a tag indicating whether the transmit data is data allowed to be re-transmitted or inhibited from being re-transmitted to a memory section. A buffer is fed with the transmit data from a data source for transmit data to the memory section. A receiver is receives data from the memory section and checks such received data for errors. Either the transmit data from the data source is coupled to the memory section in absence of a detected error or the data in the buffer is coupled to the memory section when an error has been detected and the data has been tagged with an indication that the transmit data is data allowed to be re-transmitted; selectively.

Abstract: A system analyzer for a data storage system has a control module and a memory module. The system analyzer includes a logic analyzer, an input port that couples to the data storage system, an output port that couples to the logic analyzer, and a pre-processor which is interconnected between the input port and the output port. The pre-processor is configured to receive, while a first point-to-point signal is exchanged between the control module and the memory module, a second point-to-point signal which is a copy of the first point-to-point signal. The pre-processor is further configured to generate a pre-processed signal based on the second point-to-point signal, and to provide the pre-processed signal to the logic analyzer.

Abstract: A system interface having a cache memory and a plurality of directors. Each one of the plurality of directors includes a data pipe coupled between an input of such one of the directors. The data pipe includes a data pipe memory and a data pipe memory controller for controlling the data pipe memory. Each one of the directors includes microprocessor coupled to the data pipe memory controller. The system includes a switching network coupled to the cache memory to transfer data between the memory and: (a) the input of a selected one of the plurality of directors through the data pipe memory; (b) the microprocessor and the data pipe memory through the data pipe memory controller of a selected one of the plurality of directors; and (c) the microprocessor and the data pipe memory controller while by-passing the data pipe memory of a selected one of the plurality of directors.

Abstract: An innovative roofing tile is presented, the roofing tile configured to allow liquid such as rain to flow through the roofing tile. The innovative roofing tile allows the design of a roof with ahidden gutters. Such a roof is both esthetic and allows for a low-maintenance and robust gutter system.