Patents by Inventor Ofer Sierra

Ofer Sierra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070088965
    Abstract: Periods of futile activity by one or more logic circuits of a component of a processor may be predicted, and then during each such period, one or more of the logic circuits may operate in a power-save state with reduced power consumption, with the latter part of the period being used to bring the logic circuits back into performance state, so that performance is not diminished beyond an acceptable level due to the power-save state. The decision of whether to reduce the power consumption of a particular logic circuit of a particular processor component is to have at a particular future time is made internally in the particular processor component based on one or more signals received by the particular processor component.
    Type: Application
    Filed: December 12, 2006
    Publication date: April 19, 2007
    Inventors: Zeev Sperber, Ittai Anati, Ofer Sierra, Asi Joseph, Sagi Lahav
  • Patent number: 7167989
    Abstract: Periods of futile activity by one or more logic circuits of a component of a processor may be predicted, and then during each such period, one or more of the logic circuits may operate in a power-save state with reduced power consumption, with the latter part of the period being used to bring the logic circuits back into performance state, so that performance is not diminished beyond an acceptable level due to the power-save state. The decision of whether to reduce the power consumption of a particular logic circuit of a particular processor component is to have at a particular future time is made internally in the particular processor component based on one or more signals received by the particular processor component.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: January 23, 2007
    Assignee: Intel Corporation
    Inventors: Zeev Sperber, Ittai Anati, Ofer Sierra, Asi Joseph, Sagi Lahav
  • Publication number: 20050081067
    Abstract: Periods of futile activity by one or more logic circuits of a component of a processor may be predicted, and then during each such period, one or more of the logic circuits may operate in a power-save state with reduced power consumption, with the latter part of the period being used to bring the logic circuits back into performance state, so that performance is not diminished beyond an acceptable level due to the power-save state. The decision of whether to reduce the power consumption of a particular logic circuit of a particular processor component is to have at a particular future time is made internally in the particular processor component based on one or more signals received by the particular processor component.
    Type: Application
    Filed: October 14, 2003
    Publication date: April 14, 2005
    Inventors: Zeev Sperber, Ittai Anati, Ofer Sierra, Asi Joseph, Sagi Lahav