Abstract: The invention is a method to analyze and control the spread of viral, bacterial, fungal or other infections in the form of a pandemic by collecting and analyzing data from different wide spread sources. The use of communications, a high number of sensors, the ability to geolocate and geotag measurements, and tools for trend analysis and prediction of large data amounts, allows to detect trends, green-light areas that are not infected, contain infected areas, generate recommendations, analyze the time that it takes to develop symptoms in different demographics and more.

Abstract: A graphics processing chip includes multiple graphics pipeline cores and multi-pipeline core logic circuitry to process graphic data streams received from a processor and to drive multiple GPUs on the multiple graphics pipeline cores.

Abstract: A method for controlling one or more of image resolution or FPS in graphics systems at runtime includes providing a computer system having a CPU, one or more of an integrated or a discrete GPU, a display to display images, a non-transitory computer readable system memory and at least one application running on the computer system that generates at least one of a stream of graphic library commands and/or shader codes at run time to display images at a given resolution and a given FPS; intercepting the stream of graphics library commands and/or shaders codes generated by the running application at run time. In the event that an on-the-fly change of one or more of resolution or FPS is desired for keeping a user's experience above a predefined minimal level of playability while maintaining desired power conservation, one or more of the following is modified: (a) the resolution by modification of one or more of the shader code, or graphics library commands; or (b) the FPS.

Abstract: A hub mechanism for use in a multiple graphics processing unit (GPU) system includes a hub routing unit positioned on a bus between a controller unit and multiple GPUs. The hub mechanism is used for routing data and commands over a graphic pipeline between a user interface and one or more display units. The hub mechanism also includes a hub driver for issuing commands for controlling the hub routing unit.

Abstract: A method for controlling image resolution in graphics systems at runtime is provided. In use, the stream of commands and Shaders of the running application is intercepted and analyzed at run time. In the event that an on-the-fly change of resolution is required, the change is made by modification of the Shader assembly code or of the graphics library commands.

Abstract: A method for controlling image resolution in graphics systems at runtime is provided. In use, the stream of commands and Shaders of the running application is intercepted and analyzed at run time. In the event that an on-the-fly change of resolution is required, the change is made by modification of the Shader assembly code or of the graphics library commands.

Abstract: A graphics processing chip includes multiple graphics pipeline cores and multi-pipeline core logic circuitry to process graphic data streams received from a processor and to drive multiple GPUs on the multiple graphics pipeline cores.

Abstract: A silicon chip of a monolithic construction for use in implementing a multiple core graphics processing and display subsystem in a computing system having a CPU, a system memory, an operating system (OS), a CPU bus, and a display device with a display surface. The computing system supports (i) one or more software applications for issuing graphics commands, (ii) one or more graphics libraries for storing data used to implement said graphics commands. The silicon chip comprises multiple graphic pipeline cores, a partial frame buffer for buffering pixels corresponding to image fragments, a routing center, control unit, and a display interface, for displaying composited images on the display surface of the computing system.

Abstract: A hub mechanism for use in a multiple graphics processing unit (GPU) system includes a hub routing unit positioned on a bus between a controller unit and multiple GPUs. The hub mechanism is used for routing data and commands over a graphic pipeline between a user interface and one or more display units. The hub mechanism also includes a hub driver for issuing commands for controlling the hub routing unit.

Abstract: A method of dynamic load-balancing in a PC-based computing system employing a multiple GPU-based graphics pipeline architecture supporting multiple modes of GPU parallelization. During the execution of the graphics application, the stream of geometrical data and said graphics commands is analyzed, and the mode of parallelization of the GPUs during each frame, is determined using results of the analysis of the stream of geometrical data and graphics commands, and one or more policies for determining the mode of parallelization. The stream of geometrical data and graphic commands is distributed to the GPUs according to the determined mode of parallelization. During the generation of each frame, one or more of GPUs are used to process the stream of geometrical data and graphic commands, or a portion thereof, while operating in the parallelization mode, so as to generate pixel data corresponding to at least a portion of an image of 3D object.

Abstract: A method for controlling image resolution in graphics systems at runtime is provided. In use, the stream of commands and Shaders of the running application is intercepted and analyzed at run time. In the event that an on-the-fly change of resolution is required, the change is made by modification of the Shader assembly code or of the graphics library commands.

Abstract: A graphics processing subsystem for use in a computing system, including a plurality of GPUs operating according to time division mode of graphics parallelization. At least one of the GPUs is a display-designated GPU that is connectable to a screen for displaying images produced by the graphics processing subsystem, and at least one of the GPUs is a non-display-designated GPU. The subsystem includes a hardware hub having a router, and being located between a CPU of the computing system and the plurality of GPUs. For images to be generated and displayed on the screen, the router directs to the plurality of GPUs successively a stream of geometric data and graphics commands. The geometric data and graphics commands directed to a non-display-designated GPU are processed by the GPU into image pixel data associated with a frame, the image pixel data is then redirected to the router, the image pixel data is then redirected to the display-designated GPU, and the image pixel data is then displayed on the screen.

Abstract: A silicon chip of a monolithic construction for use in implementing a multiple core graphics processing and display subsystem in a computing system having a CPU, a system memory, an operating system (OS), a CPU bus, and a display device with a display surface. The computing system supports (i) one or more software applications for issuing graphics commands, (ii) one or more graphics libraries for storing data used to implement said graphics commands. The silicon chip comprises multiple graphic pipeline cores, a partial frame buffer for buffering pixels corresponding to image fragments, a routing center, control unit, and a display interface, for displaying composited images on the display surface of the computing system.

Abstract: A PC-based computing system employing a bridge chip with a routing unit to distribute geometrical data and graphics commands to multiple GPU-driven pipeline cores supported on a plurality of graphics cards and the bridge chip. The PC-based computing system includes system memory for storing software graphics applications, software drivers and graphics libraries, and an operating system (OS), stored in the system memory, and a central processing unit (CPU) supported on a motherboard, for executing the OS, graphics applications, drivers and graphics libraries. The routing unit in the bridge chip interfaces with the CPU and the GPU-driven pipeline cores.

Abstract: A high performance graphics processing and display system architecture supporting a cluster of multiple cores of graphic processing units (GPUs) that cooperate to provide a powerful and highly scalable visualization solution supporting photo-realistic graphics capabilities for diverse applications. The present invention eliminates rendering bottlenecks along the graphics pipeline by dynamically managing various parallel rendering techniques and enabling adaptive handling of diverse graphics applications.

Abstract: A PC-based computing system employing a silicon chip having a routing unit and a control unit for parallelizing multiple GPU-driven pipeline cores according to an object division mode of parallel operation, during the running of a graphics application. The PC-based computing system includes system memory for storing software graphics applications, software drivers and graphics libraries, and an operating system (OS), stored in the system memory, and a central processing unit (CPU), for executing the OS, graphics applications, drivers and graphics libraries. The system also includes a CPU/memory interface module, a CPU bus, a silicon chip of monolithic construction interfaced with the CPU/memory interface module by way of the CPU bus.

Abstract: A PC-based computing system employing a silicon chip implementing parallelized GPU-driven pipelines cores supporting multiple modes of parallelization dynamically controlled while running a graphics application. The PC-based computing system includes system memory for storing software graphics applications, software drivers and graphics libraries, and an operating system (OS), stored in the system memory, and a central processing unit (CPU), for executing the OS, graphics applications, drivers and graphics libraries. The system also includes a CPU/memory interface module and a CPU bus. The routing unit (i) routes the stream of geometrical data and graphic commands from the graphics application to one or more of the GPU-driven pipeline cores, and (ii) routes pixel data output from one or more of GPU-driven pipeline cores during the composition of frames of pixel data corresponding to final images for display on the display surface.

Abstract: A PC-based computing system employing a silicon chip having a routing unit, a control unit and profiling unit for parallelizing multiple GPU-driven pipeline cores according to the object division mode of parallelization operation, during a graphics application. The PC-based computing system includes system memory for storing software graphics applications, software drivers and graphics libraries, and an operating system (OS), stored in the system memory, and a central processing unit (CPU), for executing the OS, graphics applications, drivers and graphics libraries. The system also includes a CPU/memory interface module and a CPU bus. The routing unit (i) routes the stream of geometrical data and graphic commands from the graphics application to one or more of the GPU-driven pipeline cores, and (ii) routes pixel data output from one or more of GPU-driven pipeline cores during the composition of frames of pixel data corresponding to final images for display on the display surface.

Abstract: A PC-based computing system capable of displaying images of 3-D objects during an interactive process between said computing system and a user thereof. The PC-based computing system includes a system memory for storing software graphics applications, software drivers and graphics libraries, and an operating system (OS), stored in the system memory, and a central processing unit (CPU), for executing the OS, graphics applications, drivers. and graphics libraries. The system also includes an CPU interface module, a PC bus, a graphics processing subsystem interfaced with the CPU interface module by way of the PC bus, and a display surface for displaying said images by graphically displaying frames of pixel data produced by the graphics processing subsystem. The graphics processing subsystem includes a plurality of GPUs arranged in a parallel architecture and operating according to a parallelization mode of operation so that the GPUs support multiple graphics pipelines and process data in a parallel manner.

Abstract: PC-based computing system having an integrated graphics subsystem supporting parallel graphics processing operations across a plurality of different graphics processing units (GPUs) supplied from the same or different vendors. The graphics subsystem include a graphics controller hub (GCH) chip located on a CPU bus, and having Multi-Pipeline Core Logic (MP-CL) circuitry including a routing unit and a control unit. The plurality of different GPUs are interfaced with the GCH chip. Each different GPU supports a GPU-driven pipeline core having a frame buffer (FB) for storing a fragment of pixel data. The GPU-driven pipeline cores are arranged in a parallel architecture and operated according to a parallelization mode of operation, so that said GPU-driven pipeline cores process data in a parallel manner.