Abstract: A power management subsystem included in a computer system may include a host device and a power circuit group. The power circuit group includes multiple power circuits arranged in a tree-like structure. The resources of the multiple power circuits are mapped to corresponding addresses within a common address space. The host device sends, via a first communication bus, commands to a branch power circuit of the multiple power circuits, which, in turn, relays the commands, using a second communication bus, to corresponding ones of the other power circuits based on respective power resources specified in the commands received from the host device.

Abstract: A power management subsystem included in a computer system may include a host device and a power circuit group. The power circuit group includes multiple power circuits arranged in a tree-like structure. The resources of the multiple power circuits are mapped to corresponding addresses within a common address space. The host device sends, via a first communication bus, commands to a branch power circuit of the multiple power circuits, which, in turn, relays the commands, using a second communication bus, to corresponding ones of the other power circuits based on respective power resources specified in the commands received from the host device.

Abstract: A power management subsystem included in a computer system may include a host device and a power circuit group. The power circuit group includes multiple power circuits arranged in a tree-like structure. The resources of the multiple power circuits are mapped to corresponding addresses within a common address space. The host device sends, via a first communication bus, commands to a branch power circuit of the multiple power circuits, which, in turn, relays the commands, using a second communication bus, to corresponding ones of the other power circuits based on respective power resources specified in the commands received from the host device.

Abstract: A power management subsystem included in a computer system may include a host device and a power circuit group. The power circuit group includes multiple power circuits arranged in a tree-like structure. The resources of the multiple power circuits are mapped to corresponding addresses within a common address space. The host device sends, via a first communication bus, commands to a branch power circuit of the multiple power circuits, which, in turn, relays the commands, using a second communication bus, to corresponding ones of the other power circuits based on respective power resources specified in the commands received from the host device.

Abstract: A power converter circuit that includes a switch node coupled to a regulated power supply node via an inductor is configured to regulate a voltage level of a power supply node using a particular one of multiple available operating modes. In response to receiving a command to reduce the voltage level of the power supply node, the power converter circuit begins to reduce the voltage level of the power supply node, while autonomously selecting different ones of available operating modes. The power converter circuit may compare to the voltage level of the power supply node to boundary levels and select a different operating mode when the voltage level of the power supply node exceeds one of the boundaries. By switching operating modes during the negative slew of the voltage level of the power supply node, the power converter may maintain a target efficiency during the reduction in voltage.

Abstract: A power converter circuit that includes a switch node coupled to a regulated power supply node via an inductor is configured to regulate a voltage level of a power supply node using a particular one of multiple available operating modes. In response to receiving a command to reduce the voltage level of the power supply node, the power converter circuit begins to reduce the voltage level of the power supply node, while autonomously selecting different ones of available operating modes. The power converter circuit may compare to the voltage level of the power supply node to boundary levels and select a different operating mode when the voltage level of the power supply node exceeds one of the boundaries. By switching operating modes during the negative slew of the voltage level of the power supply node, the power converter may maintain a target efficiency during the reduction in voltage.

Abstract: Electrical mats for generating heat, light or IR radiation which may be cut, drilled or trimmed and maintain their function. The mat is made of at least two sets of non-parallel electrodes of different polarities wherein electrodes of same polarities are connected to each other, but isolated from electrodes of different polarities; and a plurality of electrical elements connected to the electrode of different polarity and generating heat, radiation or light. The mats may be in the form of tiles, strips or tubes and may be used to tile 2D or 3D structures. The mats may also include cover layer or thermal isolation. Mats may be formed by deposition on a substrate or woven as fabric.

Abstract: Electrical mats for generating heat, light or IR radiation which may be cut, drilled or trimmed and maintain their function. The mat is made of at least two sets of non-parallel electrodes of different polarities wherein electrodes of same polarities are connected to each other, but isolated from electrodes of different polarities; and a plurality of electrical elements connected to the electrode of different polarity and generating heat, radiation or light. The mats may be in the form of tiles, strips or tubes and may be used to tile 2D or 3D structures. The mats may also include cover layer or thermal isolation. Mats may be formed by deposition on a substrate or woven as fabric.

Abstract: In one embodiment, a computer system to store application state data associated with a transaction between a client computing device and a server computing device comprises a processor, a memory module coupled to the processor and comprising logic instructions stored on a computer readable medium which, when executed by the processor, configure the processor to receive, from a capturing module that monitors transactions between one or more client computing devices and the server computing device a method, an object on which the method is being performed, and metadata associated with at least one of the object and the method, generate at least one method metadata message that uniquely identifies the method, generate at least one method invocation message that describes characteristics of a single method call, and generate at least one object instance that describes an instance of the object, and store the at least one method metadata message, the at least one method invocation message, and the at least one obj

Abstract: A processing arrangement (1) includes a processing unit (3) adapted to execute a predetermined set of processing instructions received from an instruction input (12). The set of processing instructions includes at least one predetermined processing instruction adapted to initiate a fixing operation. A memory unit (2) with a multiplicity of memory cells (5) is adapted to store data values. A detection unit (6) is adapted to detect a data value of a memory cell (5) and a data output (7) adapted to provide, on successful detection, the detected data value of a memory cell (5) or, on unsuccessful detection, a predetermined data value to the data output (7). The data output (7) is operationally coupled to the instruction input (12). The predetermined data value is mapped to the predetermined processing instruction adapted to initiate the fixing operation of an execution through the processing unit (3).

Abstract: A processing arrangement (1) includes a processing unit (3) adapted to execute a predetermined set of processing instructions received from an instruction input (12). The set of processing instructions includes at least one predetermined processing instruction adapted to initiate a fixing operation. A memory unit (2) with a multiplicity of memory cells (5) is adapted to store data values. A detection unit (6) is adapted to detect a data value of a memory cell (5) and a data output (7) adapted to provide, on successful detection, the detected data value of a memory cell (5) or, on unsuccessful detection, a predetermined data value to the data output (7). The data output (7) is operationally coupled to the instruction input (12). The predetermined data value is mapped to the predetermined processing instruction adapted to initiate the fixing operation of an execution through the processing unit (3).