Abstract: Example implementations include a method of optimizing irregular error correction code components in memory devices, a method including obtaining one or more code rate parameters including a payload size parameter, a group size parameter, and a redundancy parameter generating a first number of first code component blocks associated with a first error correction capability, and a second number of code component blocks associated with a second error correction capability aligning the first code component blocks and the second code component blocks to the group size parameter aligning the first code component blocks and the second code component blocks to a code component length constraint, and generating, in accordance with an optimization metric based on the first error correction capability and the second error correction capability, first optimized code components based on the first code component blocks and second optimized code components based on the second code component blocks.

Abstract: A flash memory system may include a flash memory and a circuit for performing operations on the flash memory. The circuit may be configured to obtain reference voltages from one or more read samples, and a plurality of sets of reference voltages. The circuit may be configured to obtain a plurality of distances, each being a distance between a point corresponding to the obtained reference voltages and a point corresponding to a respective set of reference voltages. The circuit may be configured to determine a first set of reference voltages such that a distance between the point corresponding to the obtained reference voltages and a point corresponding to the first set of reference voltage is a minimum distance of the plurality of distances. The circuit may be configured to perform read operations on locations of the flash memory with the first set of reference voltages.

Abstract: A flash memory system may include a flash memory and a circuit for performing operations on the flash memory. The circuit may be configured to obtain reference voltages from one or more read samples, and a plurality of sets of reference voltages. The circuit may be configured to obtain a plurality of distances, each being a distance between a point corresponding to the obtained reference voltages and a point corresponding to a respective set of reference voltages. The circuit may be configured to determine a first set of reference voltages such that a distance between the point corresponding to the obtained reference voltages and a point corresponding to the first set of reference voltage is a minimum distance of the plurality of distances. The circuit may be configured to perform read operations on locations of the flash memory with the first set of reference voltages.

Abstract: Various implementations described herein relate to systems and methods for detecting soft errors, including but not limited to, errors introduced after reading a codeword from a non-volatile memory, and before providing data to a host. Embodiments can include decoding the codeword from the non-volatile memory to obtain at least input data, and determining validity of the input data using a first signature after processing the input data through a data path. If it is determined that the input data is valid using the first signature, the input data is sent to a host.

Abstract: Various implementations described herein relate to systems and methods for performing error correction in a flash memory device by determining suggested corrections by decoding a codeword. In addition, whether a first set of the suggested corrections obtained based on a first component code of the plurality of component codes agree with a second set of the suggested corrections obtained based on a second component code of the plurality of component codes is determined. One of accepting the first set of the suggested corrections or rejecting the first set of the suggested corrections is selected based on whether the first set of the suggested corrections and the second set of the suggested corrections agree.

Abstract: A system for decoding data stored in a non-volatile storage device may include processing circuits configured to decode, in a first iteration, each of a plurality of component codes corresponding to the data by performing a first number of enumerations over hypotheses. The processing circuits may be configured to determine, in the first iteration, an extrinsic value output for each of the component codes based on log-likelihood ratios (LLRs) of one or more error bits of a codeword. The processing circuits may be configured to determine a second number of enumerations based on the extrinsic value. The processing circuits may be configured to decode, in a second iteration, each of the plurality of component codes by performing the second number of enumerations over hypotheses.

Abstract: A method, of decoding error correction code of a memory device with dynamic bit error estimation, can include generating at least one metric corresponding to one or more syndromes associated with a code word, the code word comprising an error correction code of a memory device, decoding the code word by a first decoder integrated with the memory device, in response to a determination that the metric satisfies a threshold associated with the syndromes, the first decoder having a first execution property, and decoding the code word by a second decoder integrated with the memory device, in response to a determination that the metric does not satisfy the threshold associated with the syndromes, the second decoder having a second execution property distinct from the first execution property, or in response to a determination that the metric satisfies the threshold associated with the syndromes, and in response to a determination to perform further decoding.

Abstract: Various implementations described herein relate to systems and methods for detecting soft errors, including but not limited to, errors introduced after reading a codeword from a non-volatile memory, and before providing data to a host. Embodiments can include decoding the codeword from the non-volatile memory to obtain at least input data, and determining validity of the input data using a first signature after processing the input data through a data path. If it is determined that the input data is valid using the first signature, the input data is sent to a host.

Abstract: Example implementations include a method of optimizing irregular error correction code components in memory devices, a method including obtaining one or more code rate parameters including a payload size parameter, a group size parameter, and a redundancy parameter generating a first number of first code component blocks associated with a first error correction capability, and a second number of code component blocks associated with a second error correction capability aligning the first code component blocks and the second code component blocks to the group size parameter aligning the first code component blocks and the second code component blocks to a code component length constraint, and generating, in accordance with an optimization metric based on the first error correction capability and the second error correction capability, first optimized code components based on the first code component blocks and second optimized code components based on the second code component blocks.

Abstract: Various implementations described herein relate to systems and methods for decoding data stored in a non-volatile storage device, including determining error candidates and determining whether at least one first error candidate from the error candidates is found based on two of the component codes agreeing on a same error candidate. In addition, whether at least one second error candidate is found based on two of the component codes agreeing on a same error candidate is determined in response to implementing a suggested correction at one of the error candidates. Errors in the data are corrected based on at least one of whether the at least one first error candidate is found or whether the at least one second error candidate is found.

Abstract: A flash memory system may include a flash memory and a circuit for decoding a result of a read operation on the flash memory using a first codeword. The circuit may be configured to generate an estimated codeword based on a result of hard decoding the first codeword and a result of hard decoding a second codeword. The circuit may be further configured to generate soft information based on the hard decoding result of the first codeword and the estimated codeword. The circuit may be further configured to decode the result of the read operation on the flash memory using the soft information.

Abstract: Various implementations described herein relate to systems and methods for decoding data stored in a non-volatile storage device, including determining error candidates and determining whether at least one first error candidate from the error candidates is found based on two of the component codes agreeing on a same error candidate. In addition, whether at least one second error candidate is found based on two of the component codes agreeing on a same error candidate is determined in response to implementing a suggested correction at one of the error candidates. Errors in the data are corrected based on at least one of whether the at least one first error candidate is found or whether the at least one second error candidate is found.

Abstract: Various implementations described herein relate to systems and methods for detecting soft errors, including but not limited to, reading a codeword from a non-volatile memory, decoding the codeword to obtain at least input data, determining validity of the input data using a first signature after processing the input data through a data path, and in response to determining that the input data is valid using the first signature, sending the input data to a host.

Abstract: Various implementations described herein relate to systems and methods for decoding data stored in a non-volatile storage device, including determining error candidates and determining whether at least one first error candidate from the error candidates is found based on two of the component codes agreeing on a same error candidate. In addition, whether at least one second error candidate is found based on two of the component codes agreeing on a same error candidate is determined in response to implementing a suggested correction at one of the error candidates. Errors in the data are corrected based on at least one of whether the at least one first error candidate is found or whether the at least one second error candidate is found.

Abstract: A flash memory system may include a flash memory and a circuit for decoding a result of a read operation on the flash memory using a first codeword. The circuit may be configured to generate first soft information of the first codeword. The circuit may be further configured to generate second soft information of a second codeword. The circuit may be configured to generate third soft information based on the first soft information and the second soft information. The circuit may be configured to decode the result of the read operation on the flash memory using the third soft information.

Abstract: Various implementations described herein relate to systems and methods for encoding data having input bits to be stored in a non-volatile storage device, including mapping the input bits to a plurality of component codes of an error correction code (ECC) and encoding the input bits as the plurality of component codes, wherein first input bits of the input bits encoded by any of the plurality of component codes are encoded by every other component code of the plurality of component codes in a non-overlapping manner.

Abstract: Various implementations described herein relate to systems and methods for performing error correction in a flash memory device by determining suggested corrections by decoding a codeword. In addition, whether a first set of the suggested corrections obtained based on a first component code of the plurality of component codes agree with a second set of the suggested corrections obtained based on a second component code of the plurality of component codes is determined. One of accepting the first set of the suggested corrections or rejecting the first set of the suggested corrections is selected based on whether the first set of the suggested corrections and the second set of the suggested corrections agree.

Abstract: Various implementations described herein relate to systems and methods for encoding data having input bits to be stored in a non-volatile storage device, including mapping the input bits to a plurality of component codes of an error correction code (ECC) and encoding the input bits as the plurality of component codes, wherein first input bits of the input bits encoded by any of the plurality of component codes are encoded by every other component code of the plurality of component codes in a non-overlapping manner.

Abstract: Apparatus, systems, methods, and articles may operate to move an output phase of a clock phase adjustment device associated with a master clock through a plurality of phase shifts relative to a phase of the master clock. A data integrity test may be performed on a serial data receive circuit clocked using an output phase of the clock phase adjustment device following each one of the plurality of phase shifts.

Abstract: In an embodiment, a phase interpolator (PI) circuit is in an integrated circuit with a test latch, and the test latch is enabled by a test clock signal to under-sample the PI output clock signal from the signal source. In a method of operation, a PI output clock signal is generated in an integrated circuit, and the PI output clock signal is under-sampled in a test latch in the integrated circuit triggered by a test clock signal. Output data from the test latch is transmitted to a test device that is separated from the integrated circuit.