Abstract: A resistance ladder comprises a plurality of resistors in series, with taps for producing comparison voltage levels for an analog-to-digital converter (ADC), coupled at its ends to reference and common voltages via first and second adjustable resistances. The reference voltage is produced by an amplifier whose gain depends on a resistance ratio that is trimmed to determine a gain or full-scale range of the ADC. Offset trimming for the ADC is provided by making equal and opposite changes to the first and second adjustable resistances, so that the full-scale range is unchanged and the offset and gain adjustments are independent of one another.

Abstract: A reset circuit produces a composite reset signal, in dependence upon a supply voltage, from reset signals produced by three reset units. A first unit produces its reset signal in dependence upon a precise voltage comparison. A second unit, operable at lower values of the supply voltage than the first unit, produces its reset signal in dependence upon the forward voltage drop of a diode. A third unit produces its reset signal in dependence upon charging of a capacitor from the supply voltage via a resistance, to maintain the composite reset signal for at least a predetermined period.