Patents by Inventor Ognjen Katic

Ognjen Katic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9444588
    Abstract: A method for evaluating operation of a receiver comprising an analog front end, a plurality of samplers connected in parallel to the analog front end, the plurality of samplers comprising a plurality of utility samplers, a plurality of data samplers and a plurality of timing samplers, an unrolled decision feedback equalizer (UDFE) connected to outputs of the plurality of data samplers, and a serial input parallel out (SIPO) block connected to an output of the UDFE and outputs of the plurality of utility and timing samplers. The method comprises adjusting settings of the plurality of utility samplers to sweep across a range of interest, at each of a plurality of points comparing a selected output of one of the plurality of utility samplers at that point to an output of one of the plurality of data samplers to detect an error event, and, accumulating the error events.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: September 13, 2016
    Inventors: Ognjen Katic, William D. Warner
  • Patent number: 9224479
    Abstract: A method is disclosed for setting or modifying a threshold voltage in a NAND flash memory, using an optimization method and based on an error, such as stored in a threshold voltage table. In an embodiment, a method is provided to optimize the read voltage on a NAND flash memory in order to minimize the errors on the NAND flash memory in the fewest reads operations as possible. Advantageously, the method of the present disclosure is more reliability as the method minimizes a Raw Bit Error Rate (RBER) on the NAND flash memory. In an embodiment, a NAND controller adjusts an existing cell read threshold voltage for a selected cell, using an iterative optimization method, based on a difference between first and second error rates, or a difference between first and second probabilities, to generate an adjusted cell read threshold voltage.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: December 29, 2015
    Assignee: PMC-Sierra US, Inc.
    Inventors: Stephen Bates, Ognjen Katic
  • Patent number: 8995518
    Abstract: Apparatus and methods mitigate a problem of equalizing communications signals that have been distorted by severe non-linearities such as clipping or harsh compression. For example, severe non-linearity occurs when signal compression or signal clipping occurs at rates above 20% of the data transmission interval. Severe non-linearities may significantly reduce system performance. Disclosed techniques selectively apply DSP equalization based on the detection of non-linearity for a present sample or one or more samples prior to the present sample. These techniques can be implemented in relatively low-cost high-speed SerDes designs to improve eye openings and reduce sensitivity to InterSymbol Interference (ISI) and to improve bit error rate (BER).
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: March 31, 2015
    Assignee: PMC-Sierra, Inc.
    Inventors: Ognjen Katic, Paul V. Yee, William D. Warner
  • Patent number: 8644369
    Abstract: Apparatus and methods generate equalizer coefficients for an equalizer of a receiver. In a high-speed receiver, received symbols can be subject to inter-symbol-interference (ISI). An equalizer can compensate for ISI and improve a bit error rate (BER). However, traditional adaptive techniques to generate coefficients for equalization can generate corrupted coefficients when equalized samples used for adaptation are based on clipped or heavily compressed signals. In certain situations, the clipping rate can be relatively high, such as over 20%. Equalizer performance is improved when the equalized symbols used directly or indirectly for adaptation are selected such that equalized symbols based on clipped input samples are not used for adaptation.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: February 4, 2014
    Assignee: PMC-Sierra, Inc.
    Inventors: Ognjen Katic, Paul V. Yee, William D. Warner
  • Patent number: 8428113
    Abstract: Apparatus and methods mitigate a problem of equalizing communications signals that have been distorted by severe non-linearities such as clipping or harsh compression. For example, severe non-linearity occurs when signal compression or signal clipping occurs at rates above 20% of the data transmission interval. Severe non-linearities may significantly reduce system performance. Disclosed techniques selectively apply DSP equalization based on the detection of non-linearity for a present sample or one or more samples prior to the present sample. These techniques can be implemented in relatively low-cost high-speed SerDes designs to improve eye openings and reduce sensitivity to InterSymbol Interference (ISI) and to improve bit error rate (BER).
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: April 23, 2013
    Assignee: PMC-Sierra, Inc.
    Inventors: Ognjen Katic, Paul V. Yee, William D. Warner
  • Patent number: 8019029
    Abstract: Disclosed is a technique for mitigating the effect of an in-band interferer in Orthogonal Frequency Division Multiplexing (OFDM) wireless or wired networks that employ soft decision Viterbi decoder in the physical layer. The technique uses an independent estimation of the signal quality, which is passed to the Viterbi algorithm decoder so that it is able to discard the corrupted subcarriers. This improves the error correction capability of the Viterbi algorithm decoder in a receiver, which leads to fewer retransmissions and into higher information throughput.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: September 13, 2011
    Assignee: PMC-Sierra, Inc.
    Inventor: Ognjen Katic
  • Patent number: 7242712
    Abstract: A decision feedback equalizer (DFE) for a receiver that can reduce jitter is disclosed. The DFE uses an equalizer structure that employs a symbol sampling operation at a decision device, also known as a slicer. In a receiver, the phase of a signal, such as an equalized signal, is typically estimated from zero crossings in the clock recovery operation. Fluctuations in these zero crossings makes phase of the reproduced clock unstable, which decreases error performance in an associated receiver. Embodiments advantageously align inter-symbol interference (ISI) canceling terms from a feedback filter (FBF) relatively well, and thereby provide equalization of a relatively large portion of a symbol period. This advantageously stabilizes the phase of an equalized signal and reduces jitter.
    Type: Grant
    Filed: March 8, 2005
    Date of Patent: July 10, 2007
    Assignee: PMC-Sierra, Inc.
    Inventor: Ognjen Katic
  • Patent number: 7177352
    Abstract: Methods and apparatus for canceling pre-cursor inter-symbol interference (ISI) are disclosed. In a digital communication system, a significant amount of noise can be attributed to the pre-cursor portion of the ISI. In a receiver, it can be relatively difficult to compensate for pre-cursor ISI in part because pre-cursor ISI is a result of one or more symbols that have yet to arrive at the receiver. One embodiment removes a portion of this ISI by using multiple detection thresholds in parallel. For example, data slicing (generation of a hard decision) can include three thresholds. These thresholds for slicing include a positive offset, a negative offset and no offset. The positive and negative offsets can correspond to the expected pre-cursor component of the data channel for which the data is transmitted or to a fraction thereof. The path with the correctly-compensated ISI is selected later.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: February 13, 2007
    Assignee: PMC-Sierra, Inc.
    Inventors: John Plasterer, Jurgen Hissen, Mathew McAdam, Anthony Eugene Zortea, Ognjen Katic
  • Patent number: 7154946
    Abstract: An equalizer for return-to-zero (RZ) signals comprises: (a) an equalizer core for equalizing the received signal; (b) a decision corrector for detecting and correcting misplaced pulses and double pulses in the equalized signal using known characteristics and properties of the RZ signal itself; and (c) an error calculator that generates an error signal for updating tap values based on the initial outputs of the equalizer core and the corrected outputs of the decision corrector. The decision corrector comprises a zero assertion counter that generates a clock synchronized with the timing of the received signal, and corrects the equalized signal by forcing zeroes in those portions of the equalized signal that the synchronized clock indicates should be “RZ” zeroes (as opposed to “data” zeroes or “data” symbols “1” or “?1”).
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: December 26, 2006
    Assignee: PMC-Sierra, Inc.
    Inventors: Ognjen Katic, Claudio Gustavo Rey
  • Patent number: 7023941
    Abstract: An apparatus and method for jointly equalizing a return to zero (RZ) signal and detecting timing errors in the RZ signal, using values or indices from equalizer taps, including a set reference tap that does not shift. A timing error detector detects a timing error based on a group delay measured from the equalizer tap information, and then adjustment circuitry modifies samples of the received RZ signal prior to their equalization to offset that timing error. Methods of modifying the samples to offset the timing error include adjusting the timing of the sampler, or adjusting the sampled data using intermediate, interpolated samples generated by a timing interpolation filter.
    Type: Grant
    Filed: March 11, 2003
    Date of Patent: April 4, 2006
    Assignee: PMC-Sierra, Inc.
    Inventors: Claudio Gustavo Rey, Jonathan Robert Gay, William Michael Lye, Ognjen Katic, Terence K. W. Lau, Jatinder Singh Chana
  • Patent number: 6269131
    Abstract: A physical channel estimator for a communication system using pilot symbols and an equalizer uses a model of the system in which the impulse response of the physical channel is considered separately from the impulse responses of the pulse shaping filters in the transmitter and receiver of the communication system. The system is modeled as if the signals were propagated first through both pulse shaping filters and then through the physical channel. To estimate the physical channel impulse response, known pilot symbols are transmitted and then sampled. The pilot symbol samples and the known impulse responses of the pulse shaping filters are then used to estimate the physical channel impulse response. In one embodiment, the physical channel impulse response is considered time-invariant over the estimation period and a sufficient number of pilot symbol samples are taken so that the system is overdetermined.
    Type: Grant
    Filed: May 28, 1998
    Date of Patent: July 31, 2001
    Assignee: Glenayre Electronics, Inc.
    Inventors: Marlo Rene Gothe, Nino Pietro Ferrario, Claudio Gustavo Rey, Ognjen Katic