Patents by Inventor Ognjen Milic-Strkalj
Ognjen Milic-Strkalj has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10438979Abstract: An image sensor includes a plurality of photodiodes disposed in a semiconductor material and a plurality of isolation structures disposed between individual photodiodes in the plurality of photodiodes. The plurality of isolation structures electrically isolate individual photodiodes in the plurality of photodiodes. A plurality of transistors are disposed proximate to the plurality of photodiodes and include a reset transistor, an amplifier transistor, and a row select transistor. An active region and a gate electrode of at least one transistor in the plurality of transistors are vertically aligned with an isolation structure in the plurality of isolation structures.Type: GrantFiled: October 3, 2018Date of Patent: October 8, 2019Assignee: OmniVision Technologies, Inc.Inventor: Ognjen Milic-Strkalj
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Publication number: 20190035833Abstract: An image sensor includes a plurality of photodiodes disposed in a semiconductor material and a plurality of isolation structures disposed between individual photodiodes in the plurality of photodiodes. The plurality of isolation structures electrically isolate individual photodiodes in the plurality of photodiodes. A plurality of transistors are disposed proximate to the plurality of photodiodes and include a reset transistor, an amplifier transistor, and a row select transistor. An active region and a gate electrode of at least one transistor in the plurality of transistors are vertically aligned with an isolation structure in the plurality of isolation structures.Type: ApplicationFiled: October 3, 2018Publication date: January 31, 2019Inventor: Ognjen Milic-Strkalj
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Patent number: 10121806Abstract: An image sensor includes a plurality of photodiodes disposed in a semiconductor material and a plurality of isolation structures disposed between individual photodiodes in the plurality of photodiodes. The plurality of isolation structures electrically isolate individual photodiodes in the plurality of photodiodes. A plurality of transistors are disposed proximate to the plurality of photodiodes and include a reset transistor, an amplifier transistor, and a row select transistor. An active region and a gate electrode of at least one transistor in the plurality of transistors are vertically aligned with an isolation structure in the plurality of isolation structures.Type: GrantFiled: September 6, 2016Date of Patent: November 6, 2018Assignee: OmniVision Technologies, Inc.Inventor: Ognjen Milic-Strkalj
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Publication number: 20180069041Abstract: An image sensor includes a plurality of photodiodes disposed in a semiconductor material and a plurality of isolation structures disposed between individual photodiodes in the plurality of photodiodes. The plurality of isolation structures electrically isolate individual photodiodes in the plurality of photodiodes. A plurality of transistors are disposed proximate to the plurality of photodiodes and include a reset transistor, an amplifier transistor, and a row select transistor. An active region and a gate electrode of at least one transistor in the plurality of transistors are vertically aligned with an isolation structure in the plurality of isolation structures.Type: ApplicationFiled: September 6, 2016Publication date: March 8, 2018Inventor: Ognjen Milic-Strkalj
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Publication number: 20050167733Abstract: A memory cell and a method for manufacturing the memory cell. The memory cell is constructed so that it has a ratio of a dimension in the direction of the bit lines to a dimension in the direction of the word line of less than one. The bit lines are formed from the first metallization system of the memory cell, which is the metallization system nearest the surface of the substrate and the silicide regions of the memory cell. The word line is formed from a metallization system above the first metallization system. Thus, the bit lines are positioned vertically between the substrate surface and the word line.Type: ApplicationFiled: February 2, 2004Publication date: August 4, 2005Inventors: William McGee, Bruce Gieseke, Ognjen Milic-Strkalj
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Patent number: 6807107Abstract: A memory system having a memory cell subject to read and write operations with shadow circuitry including a shadow cell configured to parallel operation of the memory cell. A wordline is connected to the memory cell and bitlines are connected to the memory cell and the shadow cell. Sense circuitry is connected to the bitlines for receiving data from the memory cell. An interlock cell is connected to the sense circuitry and the shadow cell to determine an occurrence of a non-redundant write operation, to provide the non-redundant write operation to the shadow cell, and to have the shadow cell prepare the bitlines for a read operation upon completion of the non-redundant write operation.Type: GrantFiled: July 2, 2002Date of Patent: October 19, 2004Assignee: Advanced Micro Devices, Inc.Inventors: William A. McGee, Ognjen Milic-Strkalj, Bruce Alan Gieseke
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Patent number: 6798712Abstract: A memory system, and method of operation therefor, is provided having memory cells for containing data, bitlines for writing data in and reading data from the memory cells, and wordlines connected to the memory cells for causing the bitlines to write data in the memory cells in response to wordline signals. A decoder is connected to the wordlines for receiving and decoding address information in response to a clock signal and an address signal to select a wordline for a write to a memory cell. Latch circuitry is connected to the decoder and the wordlines. The latch circuitry is responsive to the clock signal for providing the wordline signal to the selected wordline for the write to the memory cell and for removing the wordline signal from the selected wordline when the write to the memory cell is complete.Type: GrantFiled: July 2, 2002Date of Patent: September 28, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Bruce Alan Gieseke, William A. McGee, Ognjen Milic-Strkalj
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Publication number: 20040004901Abstract: A memory system, and method of operation therefor, is provided having memory cells for containing data, bitlines for writing data in and reading data from the memory cells, and wordlines connected to the memory cells for causing the bitlines to write data in the memory cells in response to wordline signals. A decoder is connected to the wordlines for receiving and decoding address information in response to a clock signal and an address signal to select a wordline for a write to a memory cell. Latch circuitry is connected to the decoder and the wordlines. The latch circuitry is responsive to the clock signal for providing the wordline signal to the selected wordline for the write to the memory cell and for removing the wordline signal from the selected wordline when the write to the memory cell is complete.Type: ApplicationFiled: July 2, 2002Publication date: January 8, 2004Inventors: Bruce Alan Gieseke, William A. McGee, Ognjen Milic-Strkalj
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Patent number: 6395606Abstract: A MOS semiconductor device is formed with reduced parasitic junction capacitance and reduced gate resistance. Embodiments include forming oxide sidewall spacers on side surfaces of openings in a nitride layer exposing the substrate, and performing a channel implant. A thin gate oxide layer is then thermally grown on the exposed portion of the substrate, and a relatively thin polysilicon layer is deposited on the gate oxide layer and the spacers. A metal layer, such as tungsten, is then deposited filling the opening, and planarized, as by chemical-mechanical polishing, using the nitride layer as a polish stop. Source/drain regions are thereafter formed by ion implantation, and the source/drain regions are silicided.Type: GrantFiled: July 21, 1999Date of Patent: May 28, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Carl R. Huster, Ognjen Milic-Strkalj, Emi Ishida
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Patent number: 6274501Abstract: A method is provided for directly measuring the source/drain resistance of a metal oxide semiconductor (MOS) device. Embodiments include partially deconstructing a typical MOS device by removing its gate and gate oxide from the substrate, as by etching, while preserving its gate sidewall spacer (typically silicon nitride). A sacrificial oxide spacer is formed on the nitride spacer, as by anisotropically etching a deposited oxide layer, and the area surrounding the sacrificial oxide spacer is filled with a layer of nitride. The sacrificial oxide spacer is then selectively etched to expose a portion of the main surface of the substrate and leave the nitride spacer and layer, thus creating a location near the edge of a source/drain region for a metal contact to be formed, as by chemical vapor deposition (CVD).Type: GrantFiled: February 2, 2000Date of Patent: August 14, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Concetta Riccobene, Ognjen Milic-Strkalj
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Patent number: 6096586Abstract: There is provided a MOS device with self-compensating threshold implant regions and a method of manufacturing the same which includes a semiconductor substrate, a partial first threshold implant forming a higher concentration layer, a gate oxide formed on the surface of the higher concentration layer, and a gate formed on a surface of the gate oxide. The MOS device further includes a second threshold implant for forming self-compensating implant regions in the substrate which is subsequently heated to define pockets. A third implant is performed to create lightly-doped source/drain regions. A sidewall spacer is formed on each side of the gate. A fourth implant is performed to create highly-doped source/drain regions between the lightly-doped source/drain regions and the pockets.Type: GrantFiled: October 14, 1997Date of Patent: August 1, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Ognjen Milic-Strkalj, Geoffrey Choh-Fei Yeap
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Patent number: 6080630Abstract: The present invention provides a method for forming a MOS device having self-compensating threshold adjust implants and reduced junction capacitance. A semiconductor substrate of a first conductivity type is provided. A gate oxide is formed on the surface of the semiconductor substrate, and a polysilicon gate is formed on the surface of the gate oxide. A first implant of a dopant of the first conductivity type is performed so as to form self-compensating implant regions in the semiconductor substrate on opposite sides of the gate. Disposable sidewall spacers are then formed around the polysilicon gate. A second implant of a dopant of a second conductivity type is performed so as to create highly-doped source/drain regions which are self-aligned to the sidewall spacers.Type: GrantFiled: February 3, 1999Date of Patent: June 27, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Ognjen Milic-Strkalj, Richard Rouse, Zoran Krivokapic
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Patent number: 6015740Abstract: A method of making a semiconductor device forms a gate on a substrate and provides a self-aligned diffusion source on the substrate, without the use of a mask. The diffusion source provides dopant material into the substrate. The self-aligning of the diffusion source avoids misalignment of the mask and improper doping. When the diffusion source is polysilicon or amorphous silicon, subsequent patterning and siliciding of the polysilicon forms silicided interconnect straps available for interconnecting devices on the semiconductor wafer.Type: GrantFiled: February 10, 1997Date of Patent: January 18, 2000Assignee: Advanced Micro Devices, Inc.Inventor: Ognjen Milic-Strkalj