Abstract: Systems, methods, and a computer program are disclosed. One embodiment comprises a compiler for developing verification tests of an integrated circuit. The compiler comprises an interface and a built-in self-test (BIST) emulator. The interface includes an input and an output. The interface receives and forwards operator-level instructions to the BIST emulator, which is coupled to the output. The BIST emulator simulates the operation of a BIST module within the integrated circuit.

Abstract: Systems, methods, and a computer program are disclosed. One embodiment comprises a compiler for developing verification tests of an integrated circuit. The compiler comprises an interface and a built-in self-test (BIST) emulator. The interface includes an input and an output. The interface receives and forwards operator-level instructions to the BIST emulator, which is coupled to the output. The BIST emulator simulates the operation of a BIST module within the integrated circuit.

Abstract: A method and structure facilitates the debugging and test coverage capabilities of an integrated circuit chip device under test (DUT), such as a microprocessor or a microprocessor system, while minimizing the number of observation pads of the DUT if so desired to observe-internal signals of the DUT. Internal signals of the DUT are easily observed and monitored by entry into a time-sampling mode in which N states of the DUT internal signals are successively sampled and held during N separate runs of a repeatable test to generate N partial traces that are temporarily stored. The N partial traces are driven out to one or more observation pads of the DUT and a complete trace of the signals is subsequently obtained by merging the N partial traces into a composite trace.