Patents by Inventor Oguz H. Elibol
Oguz H. Elibol has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12056906Abstract: Embodiments are generally directed to compression in machine learning and deep learning processing. An embodiment of an apparatus for compression of untyped data includes a graphical processing unit (GPU) including a data compression pipeline, the data compression pipeline including a data port coupled with one or more shader cores, wherein the data port is to allow transfer of untyped data without format conversion, and a 3D compression/decompression unit to provide for compression of untyped data to be stored to a memory subsystem and decompression of untyped data from the memory subsystem.Type: GrantFiled: September 13, 2023Date of Patent: August 6, 2024Assignee: INTEL CORPORATIONInventors: Joydeep Ray, Ben Ashbaugh, Prasoonkumar Surti, Pradeep Ramani, Rama Harihara, Jerin C. Justin, Jing Huang, Xiaoming Cui, Timothy B. Costa, Ting Gong, Elmoustapha Ould-ahmed-vall, Kumar Balasubramanian, Anil Thomas, Oguz H. Elibol, Jayaram Bobba, Guozhong Zhuang, Bhavani Subramanian, Gokce Keskin, Chandrasekaran Sakthivel, Rajesh Poornachandran
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Publication number: 20240070926Abstract: Embodiments are generally directed to compression in machine learning and deep learning processing. An embodiment of an apparatus for compression of untyped data includes a graphical processing unit (GPU) including a data compression pipeline, the data compression pipeline including a data port coupled with one or more shader cores, wherein the data port is to allow transfer of untyped data without format conversion, and a 3D compression/decompression unit to provide for compression of untyped data to be stored to a memory subsystem and decompression of untyped data from the memory subsystem.Type: ApplicationFiled: September 13, 2023Publication date: February 29, 2024Applicant: Intel CorporationInventors: Joydeep Ray, Ben Ashbaugh, Prasoonkumar Surti, Pradeep Ramani, Rama Harihara, Jerin C. Justin, Jing Huang, Xiaoming Cui, Timothy B. Costa, Ting Gong, Elmoustapha Ould-ahmed-vall, Kumar Balasubramanian, Anil Thomas, Oguz H. Elibol, Jayaram Bobba, Guozhong Zhuang, Bhavani Subramanian, Gokce Keskin, Chandrasekaran Sakthivel, Rajesh Poornachandran
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Patent number: 11798198Abstract: Embodiments are generally directed to compression in machine learning and deep learning processing. An embodiment of an apparatus for compression of untyped data includes a graphical processing unit (GPU) including a data compression pipeline, the data compression pipeline including a data port coupled with one or more shader cores, wherein the data port is to allow transfer of untyped data without format conversion, and a 3D compression/decompression unit to provide for compression of untyped data to be stored to a memory subsystem and decompression of untyped data from the memory subsystem.Type: GrantFiled: January 10, 2023Date of Patent: October 24, 2023Assignee: INTEL CORPORATIONInventors: Joydeep Ray, Ben Ashbaugh, Prasoonkumar Surti, Pradeep Ramani, Rama Harihara, Jerin C. Justin, Jing Huang, Xiaoming Cui, Timothy B. Costa, Ting Gong, Elmoustapha Ould-ahmed-vall, Kumar Balasubramanian, Anil Thomas, Oguz H. Elibol, Jayaram Bobba, Guozhong Zhuang, Bhavani Subramanian, Gokce Keskin, Chandrasekaran Sakthivel, Rajesh Poornachandran
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Publication number: 20230230289Abstract: Embodiments are generally directed to compression in machine learning and deep learning processing. An embodiment of an apparatus for compression of untyped data includes a graphical processing unit (GPU) including a data compression pipeline, the data compression pipeline including a data port coupled with one or more shader cores, wherein the data port is to allow transfer of untyped data without format conversion, and a 3D compression/decompression unit to provide for compression of untyped data to be stored to a memory subsystem and decompression of untyped data from the memory subsystem.Type: ApplicationFiled: January 10, 2023Publication date: July 20, 2023Applicant: Intel CorporationInventors: Joydeep Ray, Ben Ashbaugh, Prasoonkumar Surti, Pradeep Ramani, Rama Harihara, Jerin C. Justin, Jing Huang, Xiaoming Cui, Timothy B. Costa, Ting Gong, Elmoustapha Ould-ahmed-vall, Kumar Balasubramanian, Anil Thomas, Oguz H. Elibol, Jayaram Bobba, Guozhong Zhuang, Bhavani Subramanian, Gokce Keskin, Chandrasekaran Sakthivel, Rajesh Poornachandran
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Patent number: 11557064Abstract: Embodiments are generally directed to compression in machine learning and deep learning processing. An embodiment of an apparatus for compression of untyped data includes a graphical processing unit (GPU) including a data compression pipeline, the data compression pipeline including a data port coupled with one or more shader cores, wherein the data port is to allow transfer of untyped data without format conversion, and a 3D compression/decompression unit to provide for compression of untyped data to be stored to a memory subsystem and decompression of untyped data from the memory subsystem.Type: GrantFiled: January 23, 2020Date of Patent: January 17, 2023Inventors: Joydeep Ray, Ben Ashbaugh, Prasoonkumar Surti, Pradeep Ramani, Rama Harihara, Jerin C. Justin, Jing Huang, Xiaoming Cui, Timothy B. Costa, Ting Gong, Elmoustapha Ould-ahmed-vall, Kumar Balasubramanian, Anil Thomas, Oguz H. Elibol, Jayaram Bobba, Guozhong Zhuang, Bhavani Subramanian, Gokce Keskin, Chandrasekaran Sakthivel, Rajesh Poornachandran
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Publication number: 20200258263Abstract: Embodiments are generally directed to compression in machine learning and deep learning processing. An embodiment of an apparatus for compression of untyped data includes a graphical processing unit (GPU) including a data compression pipeline, the data compression pipeline including a data port coupled with one or more shader cores, wherein the data port is to allow transfer of untyped data without format conversion, and a 3D compression/decompression unit to provide for compression of untyped data to be stored to a memory subsystem and decompression of untyped data from the memory subsystem.Type: ApplicationFiled: January 23, 2020Publication date: August 13, 2020Applicant: Intel CorporationInventors: Joydeep Ray, Ben Ashbaugh, Prasoonkumar Surti, Pradeep Ramani, Rama Harihara, Jerin C. Justin, Jing Huang, Xiaoming Cui, Timothy B. Costa, Ting Gong, Elmoustapha Ould-ahmed-vall, Kumar Balasubramanian, Anil Thomas, Oguz H. Elibol, Jayaram Bobba, Guozhong Zhuang, Bhavani Subramanian, Gokce Keskin, Chandrasekaran Sakthivel, Rajesh Poornachandran
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Patent number: 10546393Abstract: Embodiments are generally directed to compression in machine learning and deep learning processing. An embodiment of an apparatus for compression of untyped data includes a graphical processing unit (GPU) including a data compression pipeline, the data compression pipeline including a data port coupled with one or more shader cores, wherein the data port is to allow transfer of untyped data without format conversion, and a 3D compression/decompression unit to provide for compression of untyped data to be stored to a memory subsystem and decompression of untyped data from the memory subsystem.Type: GrantFiled: December 30, 2017Date of Patent: January 28, 2020Assignee: INTEL CORPORATIONInventors: Joydeep Ray, Ben Ashbaugh, Prasoonkumar Surti, Pradeep Ramani, Rama Harihara, Jerin C. Justin, Jing Huang, Xiaoming Cui, Timothy B. Costa, Ting Gong, Elmoustapha Ould-Ahmed-Vall, Kumar Balasubramanian, Anil Thomas, Oguz H. Elibol, Jayaram Bobba, Guozhong Zhuang, Bhavani Subramanian, Gokce Keskin, Chandrasekaran Sakthivel, Rajesh Poornachandran
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Publication number: 20190206090Abstract: Embodiments are generally directed to compression in machine learning and deep learning processing. An embodiment of an apparatus for compression of untyped data includes a graphical processing unit (GPU) including a data compression pipeline, the data compression pipeline including a data port coupled with one or more shader cores, wherein the data port is to allow transfer of untyped data without format conversion, and a 3D compression/decompression unit to provide for compression of untyped data to be stored to a memory subsystem and decompression of untyped data from the memory subsystem.Type: ApplicationFiled: December 30, 2017Publication date: July 4, 2019Applicant: Intel CorporationInventors: Joydeep Ray, Ben Ashbaugh, Prasoonkumar Surti, Pradeep Ramani, Rama Harihara, Jerin C. Justin, Jing Huang, Xiaoming Cui, Timothy B. Costa, Ting Gong, Elmoustapha Ould-Ahmed-Vall, Kumar Balasubramanian, Anil Thomas, Oguz H. Elibol, Jayaram Bobba, Guozhong Zhuang, Bhavani Subramanian, Gokce Keskin, Chandrasekaran Sakthivel, Rajesh Poornachandran
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Patent number: 10203297Abstract: Described herein is a device comprising a plurality of first reaction electrodes arranged in an array, the plurality of first reaction electrodes configured to be exposed to a solution and having a capacitance; first circuitry configured to controllably connect the plurality of first reaction electrodes to a bias source and controllably disconnect the plurality of first reaction electrodes from the bias source; and second circuitry configured to measure a rate of charging or discharging of the capacitance. Also described herein is a method of using this device to sequence DNA.Type: GrantFiled: October 9, 2015Date of Patent: February 12, 2019Assignee: Intel CorporationInventors: Jonathan S. Daniels, Oguz H. Elibol, Grace M. Credo, Xing Su
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Patent number: 10132771Abstract: An apparatus including a circuit substrate including a contact in a metal layer; and a transducer including a first electrode deposited on and coupled to a sidewall of the contact and a second electrode coupled to a conductor through which voltage can be applied, wherein the second electrode includes a profile aligned to the sidewall of the contact and separated from the first electrode by a gap. A method including forming a transducer adjacent a contact in a metal layer on a substrate, the transducer including a first electrode disposed on a sidewall of the contact and a second electrode coupled to a conductor through which voltage can be applied, wherein the second electrode includes a profile aligned to the sidewall of the contact and separated from the first electrode by a gap.Type: GrantFiled: March 28, 2014Date of Patent: November 20, 2018Assignee: Intel CorporationInventor: Oguz H. Elibol
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Publication number: 20170234825Abstract: Various embodiments provide devices, methods, and systems for high throughput biomolecule detections using transducer arrays. In one embodiment, a transducer array made up of a plurality of transducer elements may be used to detect byproducts from chemical reactions that involve redox genic tags. Each transducer element may include at least a reaction chamber and a fingerprinting region configured to flow a fluid from the reaction chamber through the fingerprinting region. The reaction chamber can have a single molecule attachment region and the fingerprinting region can include at least one set of electrodes separated by a nanogap suitable for conducting redox cycling reactions. In embodiments, by flowing chamber contents, from a reaction of a latent redox tagged probe molecule, a catalyst, and a target molecule, in the reaction chamber of the at least one transducer element through the fingerprinting region, the redox cycling reactions can be detected to identify the redox-tagged biomolecules.Type: ApplicationFiled: December 13, 2016Publication date: August 17, 2017Inventors: Oguz H. ELIBOL, Grace M. CREDO, Xing SU, Madoo VARMA, Jonathan S. DANIELS, Drew HALL, Handong LI, Noureddine TAYEBI, Kai WU
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Patent number: 9690361Abstract: An analog frontend (AFE) interface is dynamically programmable based on a determined operating state. The AFE includes hardware to interface with multiple different sensors. The AFE includes analog processing hardware that can select input data from one of the multiple sensors. The analog processing hardware is coupled to a processor that computes features from the sensor, where the features represent selected operating condition information of the AFE for the sensor. The processor is to determine one of multiple discrete operating states of the AFE for the sensor based on the computed features and dynamically adjust operation of the AFE to interface with the sensor based on the determined operating state. Dynamically adjusting the operation of the AFE includes controlling a configuration of the AFE that controls how the AFE receives the input sensor data from the sensor.Type: GrantFiled: December 24, 2014Date of Patent: June 27, 2017Assignee: Intel CorporationInventors: Oguz H Elibol, Varvara Roula Kollia, Esha John, Ryan M Field
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Patent number: 9630175Abstract: Disclosed herein is a method comprising: depositing a second electrode of each of a plurality of electrode pairs onto a substrate, through an opening of one or more resist layers; depositing a strip of a sacrificial layer directly on the second electrode through the same opening of the one or more resist layer; depositing a first electrode of each of the plurality of electrode pairs directly on the strip of the sacrificial layer through the same opening of the one or more resist layer; and forming a nanogap channel by removing the strip of the sacrificial layer; wherein the strip of the sacrificial layer is sandwiched between and in direct contact with the first electrode and the second electrode before the strip is removed, and wherein at least a portion of the first electrode directly faces at least a portion of the second electrode.Type: GrantFiled: December 26, 2014Date of Patent: April 25, 2017Assignee: INTEL CORPORATIONInventors: Nisarga Naik, Oguz H. Elibol
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Publication number: 20170074819Abstract: An apparatus including a circuit substrate including a contact in a metal layer; and a transducer including a first electrode deposited on and coupled to a sidewall of the contact and a second electrode coupled to a conductor through which voltage can be applied, wherein the second electrode includes a profile aligned to the sidewall of the contact and separated from the first electrode by a gap. A method including forming a transducer adjacent a contact in a metal layer on a substrate, the transducer including a first electrode disposed on a sidewall of the contact and a second electrode coupled to a conductor through which voltage can be applied, wherein the second electrode includes a profile aligned to the sidewall of the contact and separated from the first electrode by a gap.Type: ApplicationFiled: March 28, 2014Publication date: March 16, 2017Applicants: Intel Corporation, Intel CorporationInventor: Oguz H. ELIBOL
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Patent number: 9551682Abstract: Various embodiments provide devices, methods, and systems for high throughput biomolecule detection using transducer arrays. In one embodiment, a transducer array made up of transducer elements may be used to detect byproducts from chemical reactions that involve redox genic tags. Each transducer element may include at least a reaction chamber and a fingerprinting region, configured to flow a fluid from the reaction chamber through the fingerprinting region. The reaction chamber can include a molecule attachment region and the fingerprinting region can include at least one set of electrodes separated by a nanogap for conducting redox cycling reactions. In embodiments, by flowing the chamber content obtained from a reaction of a latent redox tagged probe molecule, a catalyst, and a target molecule in the reaction chamber through the fingerprinting region, the redox cycling reactions can be detected to identify redox-tagged biomolecules.Type: GrantFiled: June 29, 2012Date of Patent: January 24, 2017Assignee: INTEL CORPORATIONInventors: Oguz H. Elibol, Grace M. Credo, Xing Su, Madoo Varma, Jonathan S. Daniels, Drew Hall, Handong Li, Noureddine Tayebi, Kai Wu
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Patent number: 9500617Abstract: Embodiments of the invention provide transducers capable of functioning as electronic sensors and redox cycling sensors. Transducers comprise two electrodes separated by a nanogap. Molecular binding regions proximate to and within the nanogap are provided. Methods of fabricating nanogap transducers and arrays of nanogap transducers are also provided. Arrays of individually addressable nanogap transducers can be disposed on integrated circuit chips and operably coupled to the integrated circuit chip.Type: GrantFiled: December 28, 2011Date of Patent: November 22, 2016Assignee: Intel CorporationInventors: Grace M. Credo, Oguz H. Elibol
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Publication number: 20160192504Abstract: Disclosed herein is a method comprising patterning a second electrode of each of a plurality of electrode pairs onto a substrate; patterning a strip of a sacrificial layer directly across the second electrode; patterning a first electrode of each of the plurality of electrode pairs directly on the strip of the sacrificial layer; forming a nanogap channel by removing the strip of the sacrificial layer; wherein the strip of the sacrificial layer is sandwiched between and in direct contact with the first electrode and the second electrode before the strip is removed, and wherein at least a portion of the first electrode directly faces at least a portion of the second electrode. The method may involve planarization (e.g., CMP). The electrode pairs may be configured such that a redox active molecule can only diffuse back and forth therebetween while it is in the portion of the nanogap channel sandwiched therebetween.Type: ApplicationFiled: December 26, 2014Publication date: June 30, 2016Inventors: Oguz H. Elibol, Nisarga Naik
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Publication number: 20160184819Abstract: Disclosed herein is a method comprising: depositing a second electrode of each of a plurality of electrode pairs onto a substrate, through an opening of one or more resist layers; depositing a strip of a sacrificial layer directly on the second electrode through the same opening of the one or more resist layer; depositing a first electrode of each of the plurality of electrode pairs directly on the strip of the sacrificial layer through the same opening of the one or more resist layer; and forming a nanogap channel by removing the strip of the sacrificial layer; wherein the strip of the sacrificial layer is sandwiched between and in direct contact with the first electrode and the second electrode before the strip is removed, and wherein at least a portion of the first electrode directly faces at least a portion of the second electrode.Type: ApplicationFiled: December 26, 2014Publication date: June 30, 2016Inventors: Nisarga Naik, Oguz H. Elibol
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Publication number: 20160187282Abstract: Disclosed herein is a device comprising an electrode pair comprising a first electrode and a second electrode; a nanogap channel; wherein a portion of the nanogap channel is sandwiched between the first electrode and the second electrode; wherein at least a portion of the first electrode directly faces at least a portion of the second electrode, across the nanogap channel; wherein the portion of the first electrode and the portion of the second electrode are exposed to an interior of the nanogap channel; and wherein the first electrode or the second electrode comprises doped diamond, silicon carbide or a combination thereof. Also disclosed herein is a method comprising forming on a carrier substrate a first material layer comprising doped diamond, silicon carbide or a combination thereof; bonding the first material layer onto an electrical circuit.Type: ApplicationFiled: December 26, 2014Publication date: June 30, 2016Inventors: Donald S. Gardner, Oguz H. Elibol
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Publication number: 20160187961Abstract: An analog frontend (AFE) interface is dynamically programmable based on a determined operating state. The AFE includes hardware to interface with multiple different sensors. The AFE includes analog processing hardware that can select input data from one of the multiple sensors. The analog processing hardware is coupled to a processor that computes features from the sensor, where the features represent selected operating condition information of the AFE for the sensor. The processor is to determine one of multiple discrete operating states of the AFE for the sensor based on the computed features and dynamically adjust operation of the AFE to interface with the sensor based on the determined operating state. Dynamically adjusting the operation of the AFE includes controlling a configuration of the AFE that controls how the AFE receives the input sensor data from the sensor.Type: ApplicationFiled: December 24, 2014Publication date: June 30, 2016Inventors: Oguz H Elibol, Varvara Roula Kollia, Esha John, Ryan M Field