Patents by Inventor Oguz H. Elibol

Oguz H. Elibol has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12056906
    Abstract: Embodiments are generally directed to compression in machine learning and deep learning processing. An embodiment of an apparatus for compression of untyped data includes a graphical processing unit (GPU) including a data compression pipeline, the data compression pipeline including a data port coupled with one or more shader cores, wherein the data port is to allow transfer of untyped data without format conversion, and a 3D compression/decompression unit to provide for compression of untyped data to be stored to a memory subsystem and decompression of untyped data from the memory subsystem.
    Type: Grant
    Filed: September 13, 2023
    Date of Patent: August 6, 2024
    Assignee: INTEL CORPORATION
    Inventors: Joydeep Ray, Ben Ashbaugh, Prasoonkumar Surti, Pradeep Ramani, Rama Harihara, Jerin C. Justin, Jing Huang, Xiaoming Cui, Timothy B. Costa, Ting Gong, Elmoustapha Ould-ahmed-vall, Kumar Balasubramanian, Anil Thomas, Oguz H. Elibol, Jayaram Bobba, Guozhong Zhuang, Bhavani Subramanian, Gokce Keskin, Chandrasekaran Sakthivel, Rajesh Poornachandran
  • Publication number: 20240070926
    Abstract: Embodiments are generally directed to compression in machine learning and deep learning processing. An embodiment of an apparatus for compression of untyped data includes a graphical processing unit (GPU) including a data compression pipeline, the data compression pipeline including a data port coupled with one or more shader cores, wherein the data port is to allow transfer of untyped data without format conversion, and a 3D compression/decompression unit to provide for compression of untyped data to be stored to a memory subsystem and decompression of untyped data from the memory subsystem.
    Type: Application
    Filed: September 13, 2023
    Publication date: February 29, 2024
    Applicant: Intel Corporation
    Inventors: Joydeep Ray, Ben Ashbaugh, Prasoonkumar Surti, Pradeep Ramani, Rama Harihara, Jerin C. Justin, Jing Huang, Xiaoming Cui, Timothy B. Costa, Ting Gong, Elmoustapha Ould-ahmed-vall, Kumar Balasubramanian, Anil Thomas, Oguz H. Elibol, Jayaram Bobba, Guozhong Zhuang, Bhavani Subramanian, Gokce Keskin, Chandrasekaran Sakthivel, Rajesh Poornachandran
  • Patent number: 11798198
    Abstract: Embodiments are generally directed to compression in machine learning and deep learning processing. An embodiment of an apparatus for compression of untyped data includes a graphical processing unit (GPU) including a data compression pipeline, the data compression pipeline including a data port coupled with one or more shader cores, wherein the data port is to allow transfer of untyped data without format conversion, and a 3D compression/decompression unit to provide for compression of untyped data to be stored to a memory subsystem and decompression of untyped data from the memory subsystem.
    Type: Grant
    Filed: January 10, 2023
    Date of Patent: October 24, 2023
    Assignee: INTEL CORPORATION
    Inventors: Joydeep Ray, Ben Ashbaugh, Prasoonkumar Surti, Pradeep Ramani, Rama Harihara, Jerin C. Justin, Jing Huang, Xiaoming Cui, Timothy B. Costa, Ting Gong, Elmoustapha Ould-ahmed-vall, Kumar Balasubramanian, Anil Thomas, Oguz H. Elibol, Jayaram Bobba, Guozhong Zhuang, Bhavani Subramanian, Gokce Keskin, Chandrasekaran Sakthivel, Rajesh Poornachandran
  • Publication number: 20230230289
    Abstract: Embodiments are generally directed to compression in machine learning and deep learning processing. An embodiment of an apparatus for compression of untyped data includes a graphical processing unit (GPU) including a data compression pipeline, the data compression pipeline including a data port coupled with one or more shader cores, wherein the data port is to allow transfer of untyped data without format conversion, and a 3D compression/decompression unit to provide for compression of untyped data to be stored to a memory subsystem and decompression of untyped data from the memory subsystem.
    Type: Application
    Filed: January 10, 2023
    Publication date: July 20, 2023
    Applicant: Intel Corporation
    Inventors: Joydeep Ray, Ben Ashbaugh, Prasoonkumar Surti, Pradeep Ramani, Rama Harihara, Jerin C. Justin, Jing Huang, Xiaoming Cui, Timothy B. Costa, Ting Gong, Elmoustapha Ould-ahmed-vall, Kumar Balasubramanian, Anil Thomas, Oguz H. Elibol, Jayaram Bobba, Guozhong Zhuang, Bhavani Subramanian, Gokce Keskin, Chandrasekaran Sakthivel, Rajesh Poornachandran
  • Patent number: 11557064
    Abstract: Embodiments are generally directed to compression in machine learning and deep learning processing. An embodiment of an apparatus for compression of untyped data includes a graphical processing unit (GPU) including a data compression pipeline, the data compression pipeline including a data port coupled with one or more shader cores, wherein the data port is to allow transfer of untyped data without format conversion, and a 3D compression/decompression unit to provide for compression of untyped data to be stored to a memory subsystem and decompression of untyped data from the memory subsystem.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: January 17, 2023
    Inventors: Joydeep Ray, Ben Ashbaugh, Prasoonkumar Surti, Pradeep Ramani, Rama Harihara, Jerin C. Justin, Jing Huang, Xiaoming Cui, Timothy B. Costa, Ting Gong, Elmoustapha Ould-ahmed-vall, Kumar Balasubramanian, Anil Thomas, Oguz H. Elibol, Jayaram Bobba, Guozhong Zhuang, Bhavani Subramanian, Gokce Keskin, Chandrasekaran Sakthivel, Rajesh Poornachandran
  • Publication number: 20200258263
    Abstract: Embodiments are generally directed to compression in machine learning and deep learning processing. An embodiment of an apparatus for compression of untyped data includes a graphical processing unit (GPU) including a data compression pipeline, the data compression pipeline including a data port coupled with one or more shader cores, wherein the data port is to allow transfer of untyped data without format conversion, and a 3D compression/decompression unit to provide for compression of untyped data to be stored to a memory subsystem and decompression of untyped data from the memory subsystem.
    Type: Application
    Filed: January 23, 2020
    Publication date: August 13, 2020
    Applicant: Intel Corporation
    Inventors: Joydeep Ray, Ben Ashbaugh, Prasoonkumar Surti, Pradeep Ramani, Rama Harihara, Jerin C. Justin, Jing Huang, Xiaoming Cui, Timothy B. Costa, Ting Gong, Elmoustapha Ould-ahmed-vall, Kumar Balasubramanian, Anil Thomas, Oguz H. Elibol, Jayaram Bobba, Guozhong Zhuang, Bhavani Subramanian, Gokce Keskin, Chandrasekaran Sakthivel, Rajesh Poornachandran
  • Patent number: 10546393
    Abstract: Embodiments are generally directed to compression in machine learning and deep learning processing. An embodiment of an apparatus for compression of untyped data includes a graphical processing unit (GPU) including a data compression pipeline, the data compression pipeline including a data port coupled with one or more shader cores, wherein the data port is to allow transfer of untyped data without format conversion, and a 3D compression/decompression unit to provide for compression of untyped data to be stored to a memory subsystem and decompression of untyped data from the memory subsystem.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: January 28, 2020
    Assignee: INTEL CORPORATION
    Inventors: Joydeep Ray, Ben Ashbaugh, Prasoonkumar Surti, Pradeep Ramani, Rama Harihara, Jerin C. Justin, Jing Huang, Xiaoming Cui, Timothy B. Costa, Ting Gong, Elmoustapha Ould-Ahmed-Vall, Kumar Balasubramanian, Anil Thomas, Oguz H. Elibol, Jayaram Bobba, Guozhong Zhuang, Bhavani Subramanian, Gokce Keskin, Chandrasekaran Sakthivel, Rajesh Poornachandran
  • Publication number: 20190206090
    Abstract: Embodiments are generally directed to compression in machine learning and deep learning processing. An embodiment of an apparatus for compression of untyped data includes a graphical processing unit (GPU) including a data compression pipeline, the data compression pipeline including a data port coupled with one or more shader cores, wherein the data port is to allow transfer of untyped data without format conversion, and a 3D compression/decompression unit to provide for compression of untyped data to be stored to a memory subsystem and decompression of untyped data from the memory subsystem.
    Type: Application
    Filed: December 30, 2017
    Publication date: July 4, 2019
    Applicant: Intel Corporation
    Inventors: Joydeep Ray, Ben Ashbaugh, Prasoonkumar Surti, Pradeep Ramani, Rama Harihara, Jerin C. Justin, Jing Huang, Xiaoming Cui, Timothy B. Costa, Ting Gong, Elmoustapha Ould-Ahmed-Vall, Kumar Balasubramanian, Anil Thomas, Oguz H. Elibol, Jayaram Bobba, Guozhong Zhuang, Bhavani Subramanian, Gokce Keskin, Chandrasekaran Sakthivel, Rajesh Poornachandran
  • Patent number: 10203297
    Abstract: Described herein is a device comprising a plurality of first reaction electrodes arranged in an array, the plurality of first reaction electrodes configured to be exposed to a solution and having a capacitance; first circuitry configured to controllably connect the plurality of first reaction electrodes to a bias source and controllably disconnect the plurality of first reaction electrodes from the bias source; and second circuitry configured to measure a rate of charging or discharging of the capacitance. Also described herein is a method of using this device to sequence DNA.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: February 12, 2019
    Assignee: Intel Corporation
    Inventors: Jonathan S. Daniels, Oguz H. Elibol, Grace M. Credo, Xing Su
  • Patent number: 10132771
    Abstract: An apparatus including a circuit substrate including a contact in a metal layer; and a transducer including a first electrode deposited on and coupled to a sidewall of the contact and a second electrode coupled to a conductor through which voltage can be applied, wherein the second electrode includes a profile aligned to the sidewall of the contact and separated from the first electrode by a gap. A method including forming a transducer adjacent a contact in a metal layer on a substrate, the transducer including a first electrode disposed on a sidewall of the contact and a second electrode coupled to a conductor through which voltage can be applied, wherein the second electrode includes a profile aligned to the sidewall of the contact and separated from the first electrode by a gap.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: November 20, 2018
    Assignee: Intel Corporation
    Inventor: Oguz H. Elibol
  • Publication number: 20170234825
    Abstract: Various embodiments provide devices, methods, and systems for high throughput biomolecule detections using transducer arrays. In one embodiment, a transducer array made up of a plurality of transducer elements may be used to detect byproducts from chemical reactions that involve redox genic tags. Each transducer element may include at least a reaction chamber and a fingerprinting region configured to flow a fluid from the reaction chamber through the fingerprinting region. The reaction chamber can have a single molecule attachment region and the fingerprinting region can include at least one set of electrodes separated by a nanogap suitable for conducting redox cycling reactions. In embodiments, by flowing chamber contents, from a reaction of a latent redox tagged probe molecule, a catalyst, and a target molecule, in the reaction chamber of the at least one transducer element through the fingerprinting region, the redox cycling reactions can be detected to identify the redox-tagged biomolecules.
    Type: Application
    Filed: December 13, 2016
    Publication date: August 17, 2017
    Inventors: Oguz H. ELIBOL, Grace M. CREDO, Xing SU, Madoo VARMA, Jonathan S. DANIELS, Drew HALL, Handong LI, Noureddine TAYEBI, Kai WU
  • Patent number: 9690361
    Abstract: An analog frontend (AFE) interface is dynamically programmable based on a determined operating state. The AFE includes hardware to interface with multiple different sensors. The AFE includes analog processing hardware that can select input data from one of the multiple sensors. The analog processing hardware is coupled to a processor that computes features from the sensor, where the features represent selected operating condition information of the AFE for the sensor. The processor is to determine one of multiple discrete operating states of the AFE for the sensor based on the computed features and dynamically adjust operation of the AFE to interface with the sensor based on the determined operating state. Dynamically adjusting the operation of the AFE includes controlling a configuration of the AFE that controls how the AFE receives the input sensor data from the sensor.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: June 27, 2017
    Assignee: Intel Corporation
    Inventors: Oguz H Elibol, Varvara Roula Kollia, Esha John, Ryan M Field
  • Patent number: 9630175
    Abstract: Disclosed herein is a method comprising: depositing a second electrode of each of a plurality of electrode pairs onto a substrate, through an opening of one or more resist layers; depositing a strip of a sacrificial layer directly on the second electrode through the same opening of the one or more resist layer; depositing a first electrode of each of the plurality of electrode pairs directly on the strip of the sacrificial layer through the same opening of the one or more resist layer; and forming a nanogap channel by removing the strip of the sacrificial layer; wherein the strip of the sacrificial layer is sandwiched between and in direct contact with the first electrode and the second electrode before the strip is removed, and wherein at least a portion of the first electrode directly faces at least a portion of the second electrode.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: April 25, 2017
    Assignee: INTEL CORPORATION
    Inventors: Nisarga Naik, Oguz H. Elibol
  • Publication number: 20170074819
    Abstract: An apparatus including a circuit substrate including a contact in a metal layer; and a transducer including a first electrode deposited on and coupled to a sidewall of the contact and a second electrode coupled to a conductor through which voltage can be applied, wherein the second electrode includes a profile aligned to the sidewall of the contact and separated from the first electrode by a gap. A method including forming a transducer adjacent a contact in a metal layer on a substrate, the transducer including a first electrode disposed on a sidewall of the contact and a second electrode coupled to a conductor through which voltage can be applied, wherein the second electrode includes a profile aligned to the sidewall of the contact and separated from the first electrode by a gap.
    Type: Application
    Filed: March 28, 2014
    Publication date: March 16, 2017
    Applicants: Intel Corporation, Intel Corporation
    Inventor: Oguz H. ELIBOL
  • Patent number: 9551682
    Abstract: Various embodiments provide devices, methods, and systems for high throughput biomolecule detection using transducer arrays. In one embodiment, a transducer array made up of transducer elements may be used to detect byproducts from chemical reactions that involve redox genic tags. Each transducer element may include at least a reaction chamber and a fingerprinting region, configured to flow a fluid from the reaction chamber through the fingerprinting region. The reaction chamber can include a molecule attachment region and the fingerprinting region can include at least one set of electrodes separated by a nanogap for conducting redox cycling reactions. In embodiments, by flowing the chamber content obtained from a reaction of a latent redox tagged probe molecule, a catalyst, and a target molecule in the reaction chamber through the fingerprinting region, the redox cycling reactions can be detected to identify redox-tagged biomolecules.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: January 24, 2017
    Assignee: INTEL CORPORATION
    Inventors: Oguz H. Elibol, Grace M. Credo, Xing Su, Madoo Varma, Jonathan S. Daniels, Drew Hall, Handong Li, Noureddine Tayebi, Kai Wu
  • Patent number: 9500617
    Abstract: Embodiments of the invention provide transducers capable of functioning as electronic sensors and redox cycling sensors. Transducers comprise two electrodes separated by a nanogap. Molecular binding regions proximate to and within the nanogap are provided. Methods of fabricating nanogap transducers and arrays of nanogap transducers are also provided. Arrays of individually addressable nanogap transducers can be disposed on integrated circuit chips and operably coupled to the integrated circuit chip.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: November 22, 2016
    Assignee: Intel Corporation
    Inventors: Grace M. Credo, Oguz H. Elibol
  • Publication number: 20160192504
    Abstract: Disclosed herein is a method comprising patterning a second electrode of each of a plurality of electrode pairs onto a substrate; patterning a strip of a sacrificial layer directly across the second electrode; patterning a first electrode of each of the plurality of electrode pairs directly on the strip of the sacrificial layer; forming a nanogap channel by removing the strip of the sacrificial layer; wherein the strip of the sacrificial layer is sandwiched between and in direct contact with the first electrode and the second electrode before the strip is removed, and wherein at least a portion of the first electrode directly faces at least a portion of the second electrode. The method may involve planarization (e.g., CMP). The electrode pairs may be configured such that a redox active molecule can only diffuse back and forth therebetween while it is in the portion of the nanogap channel sandwiched therebetween.
    Type: Application
    Filed: December 26, 2014
    Publication date: June 30, 2016
    Inventors: Oguz H. Elibol, Nisarga Naik
  • Publication number: 20160184819
    Abstract: Disclosed herein is a method comprising: depositing a second electrode of each of a plurality of electrode pairs onto a substrate, through an opening of one or more resist layers; depositing a strip of a sacrificial layer directly on the second electrode through the same opening of the one or more resist layer; depositing a first electrode of each of the plurality of electrode pairs directly on the strip of the sacrificial layer through the same opening of the one or more resist layer; and forming a nanogap channel by removing the strip of the sacrificial layer; wherein the strip of the sacrificial layer is sandwiched between and in direct contact with the first electrode and the second electrode before the strip is removed, and wherein at least a portion of the first electrode directly faces at least a portion of the second electrode.
    Type: Application
    Filed: December 26, 2014
    Publication date: June 30, 2016
    Inventors: Nisarga Naik, Oguz H. Elibol
  • Publication number: 20160187282
    Abstract: Disclosed herein is a device comprising an electrode pair comprising a first electrode and a second electrode; a nanogap channel; wherein a portion of the nanogap channel is sandwiched between the first electrode and the second electrode; wherein at least a portion of the first electrode directly faces at least a portion of the second electrode, across the nanogap channel; wherein the portion of the first electrode and the portion of the second electrode are exposed to an interior of the nanogap channel; and wherein the first electrode or the second electrode comprises doped diamond, silicon carbide or a combination thereof. Also disclosed herein is a method comprising forming on a carrier substrate a first material layer comprising doped diamond, silicon carbide or a combination thereof; bonding the first material layer onto an electrical circuit.
    Type: Application
    Filed: December 26, 2014
    Publication date: June 30, 2016
    Inventors: Donald S. Gardner, Oguz H. Elibol
  • Publication number: 20160187961
    Abstract: An analog frontend (AFE) interface is dynamically programmable based on a determined operating state. The AFE includes hardware to interface with multiple different sensors. The AFE includes analog processing hardware that can select input data from one of the multiple sensors. The analog processing hardware is coupled to a processor that computes features from the sensor, where the features represent selected operating condition information of the AFE for the sensor. The processor is to determine one of multiple discrete operating states of the AFE for the sensor based on the computed features and dynamically adjust operation of the AFE to interface with the sensor based on the determined operating state. Dynamically adjusting the operation of the AFE includes controlling a configuration of the AFE that controls how the AFE receives the input sensor data from the sensor.
    Type: Application
    Filed: December 24, 2014
    Publication date: June 30, 2016
    Inventors: Oguz H Elibol, Varvara Roula Kollia, Esha John, Ryan M Field