Abstract: A computer implemented method for speeding up execution of a convex optimization operation one or more quadratic complexity operations to be performed by an analog crossbar hardware switch, and identifying one or more linear complexity operations to be performed by a CPU. At least one of the quadratic complexity operations is performed by the analog crossbar hardware, and at least one of the linear complexity operations is performed by the CPU. An iteration of an approximation of a solution to the convex optimization operation is updated by the CPU.

Abstract: Provided are embodiments for a computer-implemented method, a system, and a computer program product for updating analog crossbar arrays. The embodiments include receiving a number used in matrix multiplication to represent using pulse generation for a crossbar array, and receiving a first bit-length to represent the number, wherein the bit-length is a modifiable bit length. The embodiments also include selecting pulse positions in a pulse sequence having the first bit length to represent the number, performing a computation using the selected pulse positions in the pulse sequence, and updating the crossbar array using the computation.

Abstract: Methods and systems for solving a linear system include setting resistances in an array of settable electrical resistances in accordance with values of an input matrix. A series of input vectors is applied to the array as voltages to generate a series of respective output vectors. Each input vector in the series of vectors is updated based on comparison of the respective output vectors to a target vector. A solution of a linear system is determined that includes the input matrix based on the updated input vectors.

Abstract: A computer-implemented method is presented for performing matrix sketching by employing an analog crossbar architecture. The method includes low rank updating a first matrix for a first period of time, copying the first matrix into a dynamic correction computing device, switching to a second matrix to low rank update the second matrix for a second period of time, as the second matrix is low rank updated, feeding the first matrix with first stochastic pulses to reset the first matrix back to a first matrix symmetry point, copying the second matrix into the dynamic correction computing device, switching back to the first matrix to low rank update the first matrix for a third period of time, and as the first matrix is low rank updated, feeding the second matrix with second stochastic pulses to reset the second matrix back to a second matrix symmetry point.

Abstract: Techniques are provided to implement hardware accelerated computing of eigenpairs of a matrix. For example, a system includes a processor, and a resistive processing unit coupled to the processor. The resistive processing unit includes an array of cells which include respective resistive devices, wherein at least a portion of the resistive devices are tunable to encode values of a given matrix which is storable in the array of cells. When the given matrix is stored in the array of cells, the processor is configured to determine an eigenvector of the stored matrix by executing a process which includes performing analog matrix-vector multiplication operations on the stored matrix to converge an initial vector to an estimate of the eigenvector of the stored matrix.

Abstract: Described are CMOS-compatible protonic resistive devices (e.g., processing elements and/or memory elements). In embodiments, a protonic resistive memory can be formed from a proton-sensitive metal oxide channel where the concentration of protons intercalated inside the layer is controlled to modulate its conductivity. The protons can initially be supplied to the material stack by an implantation method. Irradiation techniques can be implemented to increase the concentration and conductivity of protons inside the materials. Some designs can put the active layer and reservoir in direct contact, creating an electrolyte-free device. Designs provide scalable solutions for full-scale Si-integration.

Abstract: Provided are embodiments for a computer-implemented method, a system, and a computer program product for updating an analog crossbar array. Embodiment include receiving a number used in matrix multiplication to represent using pulse generation for a crossbar array, and receiving a bit-length to represent the number. Embodiments also include selecting pulse positions in a pulse sequence having the bit length to represent the number, performing a computation using the selected pulse positions in the pulse sequence, and updating the crossbar array using the computation.

Abstract: Described are CMOS-compatible protonic resistive devices (e.g., processing elements and/or memory elements). In embodiments, a protonic resistive memory can be formed from a proton-sensitive metal oxide channel where the concentration of protons intercalated inside the layer is controlled to modulate its conductivity. The protons can initially be supplied to the material stack by an implantation method. Irradiation techniques can be implemented to increase the concentration and conductivity of protons inside the materials. Some designs can put the active layer and reservoir in direct contact, creating an electrolyte-free device. Designs provide scalable solutions for full-scale Si-integration.

Abstract: Matrix inversion systems and methods are implemented using an analog resistive processing unit (RPU) array for hardware accelerated computing. A request is received from an application to compute an inverse matrix of a given matrix, and a matrix inversion process is performed in response to the received request. The matrix inversion process includes storing a first estimated inverse matrix of the given matrix in an array RPU cells, performing a first iterative process on the first estimated inverse matrix stored in the array of RPU cells to converge the first estimated inverse matrix to a second estimated inverse matrix of the given matrix, and reading the second estimated inverse matrix from the array of RPU cells upon completion of the first iterative process. An inverse matrix is returned to the application, wherein the returned inverse matrix is based, at least in part, on the second estimated inverse matrix.

Abstract: Methods and systems for solving a linear system include setting resistances in an array of settable electrical resistances in accordance with values of an input matrix. A series of input vectors is applied to the array as voltages to generate a series of respective output vectors. Each input vector in the series of vectors is updated based on comparison of the respective output vectors to a target vector. A solution of a linear system is determined that includes the input matrix based on the updated input vectors.

Abstract: A computer-implemented method for Eigenpair computation is provided. The method includes computing, her a hardware processor, an Eigenvector and respective Eigenvalues of the Eigenvector of a matrix by using a modified Stochastic Optimization process including performing a matrix vector product on a Resistive Processing Unit (RPU) crossbar array operatively coupled to the hardware processor and performing a scalar vector product on a digital device operatively coupled to the hardware processor and representing, for each of an Eigenpair, an initial guess for the Eigenvector and the respective Eigenvalues. The computing step includes storing the matrix in the RPU crossbar array.

Abstract: A computer implemented method for speeding up execution of a convex optimization operation one or more quadratic complexity operations to be performed by an analog crossbar hardware switch, and identifying one or more linear complexity operations to be performed by a CPU. At least one of the quadratic complexity operations is performed by the analog crossbar hardware, and at least one of the linear complexity operations is performed by the CPU. An iteration of an approximation of a solution to the convex optimization operation is updated by the CPU.

Abstract: Provided are embodiments for a computer-implemented method, a system, and a computer program product for updating an analog crossbar array. Embodiment include receiving a number used in matrix multiplication to represent using pulse generation for a crossbar array, and receiving a bit-length to represent the number. Embodiments also include selecting pulse positions in a pulse sequence having the bit length to represent the number, performing a computation using the selected pulse positions in the pulse sequence, and updating the crossbar array using the computation.

Abstract: Provided are embodiments for a computer-implemented method, a system, and a computer program product for updating analog crossbar arrays. The embodiments include receiving a number used in matrix multiplication to represent using pulse generation for a crossbar array, and receiving a first bit-length to represent the number, wherein the bit-length is a modifiable bit length. The embodiments also include selecting pulse positions in a pulse sequence having the first bit length to represent the number, performing a computation using the selected pulse positions in the pulse sequence, and updating the crossbar array using the computation.

Abstract: A computer-implemented method for Eigenpair computation is provided. The method includes computing an Eigenvector and respective Eigenvalues of the Eigenvector by using a Stochastic Optimization process. The computing step includes storing the matrix in a Resistive Processing Unit (RPU) crossbar array.

Abstract: Apparatus and methods relating to programmable superconducting cells are described. A programmable superconducting cell can be formed from a superconducting current loop having at least two terminals connected to the loop. The current loop and terminals can be formed from a single layer of superconducting material. The programmable superconducting cell can be incorporated into a crossbar architecture to form a high-speed vector-matrix multiplying processor for deep neural network computations.

Abstract: A computer-implemented method is presented for performing matrix sketching by employing an analog crossbar architecture. The method includes low rank updating a first matrix for a first period of time, copying the first matrix into a dynamic correction computing device, switching to a second matrix to low rank update the second matrix for a second period of time, as the second matrix is low rank updated, feeding the first matrix with first stochastic pulses to reset the first matrix back to a first matrix symmetry point, copying the second matrix into the dynamic correction computing device, switching back to the first matrix to low rank update the first matrix for a third period of time, and as the first matrix is low rank updated, feeding the second matrix with second stochastic pulses to reset the second matrix back to a second matrix symmetry point.

Abstract: Aspects of the invention include performing a stochastic update for a crossbar array by generating a set of stochastic pulses for a crossbar array, the crossbar array including a plurality of row wires and a plurality of column wires, the plurality of row wires including a first row wire and the plurality of column wires including a first column wire, wherein a three terminal device is coupled to the first row wire and the first column wire at a crosspoint of the first row wire and the first column wire, and wherein a resistivity of the three terminal device is modified responsive to a coincidence of pulses from the set of stochastic pulses at the crosspoint of the first row and the first column, and wherein at least one terminal in the three terminal device is floating.

Abstract: A computer-implemented method and computer processing system are provided for update management for a neural network. The method includes performing an isotropic update process on the neural network using a Resistive Processing Unit. The isotropic update process uses a multiplicand and a multiplier from a multiplication operation. The performing step includes scaling the multiplicand and the multiplier to have a same order of magnitude.

Abstract: A device that is a combination of a superconducting nanowire single-photon detector and a superconducting multi-level memory. These devices can be used to count a number of photons impinging on the device through single-photon to single-flux conversion. Electrical characterization of the device demonstrates single-flux quantum (SFQ) separated states. Optical measurements using attenuated laser pulses with different mean photon number, pulse energies and repetition rates are shown to differentiate single-photon detection from other possible phenomena, such as multiphoton detection and thermal activation. Array devices and methods are also discussed.