Patents by Inventor Oh-Jung Kwon

Oh-Jung Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10589753
    Abstract: A warning system for a hearing-impaired person of a vehicle includes: a sound sensing unit disposed at a vehicle to sense sound outside of the vehicle; a database storing characteristic information of a plurality of specific sounds and visual information corresponding to the characteristic information of the plurality of specific sounds; an output unit outputting visual information corresponding to the plurality of specific sounds; and a controller extracting characteristic information of the sound sensed by the sound sensing units. In particular, the controller determines a type of the sensed sound by comparing the extracted characteristic information of the sensed sound with the characteristic information of the plurality of specific sounds stored in the database, and outputs visual information corresponding to the determined type of the sensed sound through the output unit.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: March 17, 2020
    Assignees: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATION
    Inventors: Jun Young Kwon, Seong Hyeon Lee, Oh Sol Kwon, Joo Hwan Lee, Jong Won Kim, Hyeong Jun Park, Ji In Jung
  • Publication number: 20190359229
    Abstract: A warning system for a hearing-impaired person of a vehicle includes: a sound sensing unit disposed at a vehicle to sense sound outside of the vehicle; a database storing characteristic information of a plurality of specific sounds and visual information corresponding to the characteristic information of the plurality of specific sounds; an output unit outputting visual information corresponding to the plurality of specific sounds; and a controller extracting characteristic information of the sound sensed by the sound sensing units. In particular, the controller determines a type of the sensed sound by comparing the extracted characteristic information of the sensed sound with the characteristic information of the plurality of specific sounds stored in the database, and outputs visual information corresponding to the determined type of the sensed sound through the output unit.
    Type: Application
    Filed: October 22, 2018
    Publication date: November 28, 2019
    Applicants: Hyundai Motor Company, KIA Motors Corporation
    Inventors: Jun Young KWON, Seong Hyeon LEE, Oh Sol KWON, Joo Hwan LEE, Jong Won KIM, Hyeong Jun PARK, Ji In JUNG
  • Publication number: 20190315227
    Abstract: A vehicle including a communication system for a disabled person may include: a motion capture unit that recognizes sign language of a passenger of the vehicle; an input unit that receives a voice or characters from the passenger; a database that stores sign language information; a control unit that is communicatively coupled to the motion capture unit and the input unit, the control unit being configured to translate the sign language recognized by the motion capture unit using the sign language information stored in the database, and to convert a voice received through the input unit into characters; and an output unit that is communicatively coupled to the control unit, the output unit being configured to output the sign language translated by the control unit as a voice or characters, and to output the voice converted by the control unit as characters.
    Type: Application
    Filed: October 9, 2018
    Publication date: October 17, 2019
    Inventors: Jong Won Kim, Seong Hyeon Lee, Oh Sol Kwon, Joo Hwan Lee, Hyeong Jun Park, Ji In Jung, Jun Young Kwon
  • Patent number: 10192887
    Abstract: The migration of dislocations into pristine single crystal material during crystal growth of an adjacent conductive strap is inhibited by a conductive barrier formed at the interface between the layers. The conductive barrier may be formed by implanting carbon impurities or depositing Si:C layer that inhibits dislocation movement across the barrier layer, or by forming a passivation layer by annealing in vacuum prior to deposition of amorphous Si to prevent polycrystalline nucleation at the surface of single crystalline Si, or by implanting nucleation promoting species to enhance the nucleation of polycrystalline Si away from single crystalline Si.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: January 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yun Y. Wang, Oh-Jung Kwon, Stephen G. Fugardi, Sean M. Dillon
  • Patent number: 10170304
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to self-aligned nanotube structures and methods of manufacture. The structure includes at least one nanotube structure supported by a plurality of spacers and an insulator material between the spacers and contacting the at least one nanotube structure.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: January 1, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Oh-Jung Kwon, Claude Ortolland, Dominic Schepis, Christopher Collins
  • Patent number: 10115725
    Abstract: A hard mask material is removed from an SOI substrate without using a chemical mechanical polish (CMP) process. A blocking material is deposited on a hard mask material after a deep trench reactive ion etch (RIE) process. The blocking material on top of the hard mask material is removed. A selective wet etching process is used to remove the hard mask material. Trench recess depth is effectively controlled.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: October 30, 2018
    Assignee: International Business Machines Corporation
    Inventor: Oh-Jung Kwon
  • Patent number: 10008421
    Abstract: A method includes measuring a difference between a primary X-ray diffraction peak and a secondary X-ray diffraction peak, the primary X-ray diffraction peak corresponds to an unstrained portion of a semiconductor substrate and the secondary X-ray diffraction peak corresponds to a strained portion of the semiconductor substrate, the difference between the primary X-ray diffraction peak and the secondary X-ray diffraction peak includes a delta shift peak that corresponds to changes in a crystal lattice caused by a stress applied to the strained portion of the semiconductor substrate, the delta shift peak includes variations in a deep trench capacitance.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: June 26, 2018
    Assignee: International Business Machines Corporation
    Inventors: Donghun Kang, Kriteshwar K. Kohli, Oh-jung Kwon, Anita Madan, Conal E. Murray
  • Publication number: 20180158748
    Abstract: A heat dissipation apparatus for a semiconductor module according to an exemplary embodiment of the present invention includes: a heatsink which is provided to be in surface-to-surface contact with a semiconductor module; a duct unit which includes a pair of wall members which extends perpendicularly to an edge of the other surface of the heatsink and a quadrangular box member which is formed in a quadrangular box shape opened at both ends thereof, in which two sides of the opened ends of the quadrangular box member are connected to the wall members, respectively, and any one surface, among surfaces for constituting the quadrangular box shape, is formed to be inclined; and an intake fan which is provided at the other end of the quadrangular box member, in which a vent hole is formed in the inclined lateral surface of the quadrangular box member.
    Type: Application
    Filed: July 25, 2017
    Publication date: June 7, 2018
    Inventor: Oh Jung Kwon
  • Publication number: 20180096904
    Abstract: A method includes measuring a difference between a primary X-ray diffraction peak and a secondary X-ray diffraction peak, the primary X-ray diffraction peak corresponds to an unstrained portion of a semiconductor substrate and the secondary X-ray diffraction peak corresponds to a strained portion of the semiconductor substrate, the difference between the primary X-ray diffraction peak and the secondary X-ray diffraction peak includes a delta shift peak that corresponds to changes in a crystal lattice caused by a stress applied to the strained portion of the semiconductor substrate, the delta shift peak includes variations in a deep trench capacitance.
    Type: Application
    Filed: December 5, 2017
    Publication date: April 5, 2018
    Inventors: Donghun Kang, Kriteshwar K. Kohli, Oh-jung Kwon, Anita Madan, Conal E. Murray
  • Publication number: 20180090516
    Abstract: The migration of dislocations into pristine single crystal material during crystal growth of an adjacent conductive strap is inhibited by a conductive barrier formed at the interface between the layers. The conductive barrier may be formed by implanting carbon impurities or depositing Si:C layer that inhibits dislocation movement across the barrier layer, or by forming a passivation layer by annealing in vacuum prior to deposition of amorphous Si to prevent polycrystalline nucleation at the surface of single crystalline Si, or by implanting nucleation promoting species to enhance the nucleation of polycrystalline Si away from single crystalline Si.
    Type: Application
    Filed: November 20, 2017
    Publication date: March 29, 2018
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Yun Y. Wang, Oh-Jung Kwon, Stephen G. Fugardi, Sean M. Dillon
  • Publication number: 20180022973
    Abstract: Disclosed is an acrylic adhesive, including an acrylic polymer obtained by polymerizing a mixture of about 120 parts by weight to about 250 parts by weight of acrylic monomers with about 0.1 parts by weight to about 1 parts by weight of an azo initiator, about 0.5 parts by weight to about 1 parts by weight of a filler, about 1.5 parts by weight to about 2.5 parts by weight of a crosslinking agent, and about 0.5 parts by weight to 1 parts by weight of an anti-static agent.
    Type: Application
    Filed: July 20, 2017
    Publication date: January 25, 2018
    Inventors: Sung KIM, Hyun Sook KIM, Jang Hwan JEONG, Sung Chan JO, Kyung Lae RHO, Soo Im JEONG, Oh Jung KWON, Sung Hwan KIM, Oh Nam KWON, Jae Gwan LEE, Jung Hun KIM
  • Patent number: 9870960
    Abstract: A method includes measuring a difference between a primary X-ray diffraction peak and a secondary X-ray diffraction peak, the primary X-ray diffraction peak corresponds to an unstrained portion of a semiconductor substrate and the secondary X-ray diffraction peak corresponds to a strained portion of the semiconductor substrate, the difference between the primary X-ray diffraction peak and the secondary X-ray diffraction peak includes a delta shift peak that corresponds to changes in a crystal lattice caused by a stress applied to the strained portion of the semiconductor substrate, the delta shift peak includes variations in a deep trench capacitance.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: January 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Donghun Kang, Kriteshwar K. Kohli, Oh-jung Kwon, Anita Madan, Conal E. Murray
  • Patent number: 9853055
    Abstract: The migration of dislocations into pristine single crystal material during crystal growth of an adjacent conductive strap is inhibited by a conductive barrier formed at the interface between the layers. The conductive barrier may be formed by implanting carbon impurities or depositing Si:C layer that inhibits dislocation movement across the barrier layer, or by forming a passivation layer by annealing in vacuum prior to deposition of amorphous Si to prevent polycrystalline nucleation at the surface of single crystalline Si, or by implanting nucleation promoting species to enhance the nucleation of polycrystalline Si away from single crystalline Si.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: December 26, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yun Y. Wang, Oh-Jung Kwon, Stephen G. Fugardi, Sean M. Dillon
  • Publication number: 20170287942
    Abstract: The migration of dislocations into pristine single crystal material during crystal growth of an adjacent conductive strap is inhibited by a conductive barrier formed at the interface between the layers. The conductive barrier may be formed by implanting carbon impurities or depositing Si:C layer that inhibits dislocation movement across the barrier layer, or by forming a passivation layer by annealing in vacuum prior to deposition of amorphous Si to prevent polycrystalline nucleation at the surface of single crystalline Si, or by implanting nucleation promoting species to enhance the nucleation of polycrystalline Si away from single crystalline Si.
    Type: Application
    Filed: March 30, 2016
    Publication date: October 5, 2017
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Yun Y. Wang, Oh-Jung Kwon, Stephen G. Fugardi, Sean M. Dillon
  • Publication number: 20160178679
    Abstract: A method includes measuring a difference between a primary X-ray diffraction peak and a secondary X-ray diffraction peak, the primary X-ray diffraction peak corresponds to an unstrained portion of a semiconductor substrate and the secondary X-ray diffraction peak corresponds to a strained portion of the semiconductor substrate, the difference between the primary X-ray diffraction peak and the secondary X-ray diffraction peak includes a delta shift peak that corresponds to changes in a crystal lattice caused by a stress applied to the strained portion of the semiconductor substrate, the delta shift peak includes variations in a deep trench capacitance.
    Type: Application
    Filed: December 18, 2014
    Publication date: June 23, 2016
    Inventors: Donghun Kang, Kriteshwar K. Kohli, Oh-jung Kwon, Anita Madan, Conal E. Murray
  • Patent number: 9269607
    Abstract: Embodiments of the present invention provide structures and methods for controlling stress in semiconductor wafers during fabrication. Features such as deep trenches (DTs) used in circuit elements such as trench capacitors impart stress on a wafer that is proportional to the surface area of the DTs. In embodiments, a corresponding pattern of dummy (non-functional) DTs is formed on the back side of the wafer to counteract the electrically functional DTs formed on the front side of a wafer. In some embodiments, the corresponding pattern on the back side is a mirror pattern that matches the functional (front side) pattern in size, placement, and number. By creating the minor pattern on both sides of the wafer, the stresses on the front and back of the wafer are in balance. This helps reduce topography issues such as warping that can cause problems during wafer fabrication.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: February 23, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Edward Engbrecht, Donghun Kang, Rishikesh Krishnan, Oh-jung Kwon, Karen A. Nummy
  • Patent number: 9240452
    Abstract: An array or moat isolation structure for eDRAM with heterogeneous deep trench fill and methods of manufacture is provided. The method includes forming a deep trench for a memory array and an isolation region. The method further includes forming a node dielectric on exposed surfaces of the deep trench for the memory array and the isolation region. The method further includes filling remaining portions of the deep trench for the memory array with a metal, and lining the deep trench of the isolation region with the metal. The method further includes filling remaining portions of the deep trench for the isolation region with a material, on the metal within the deep trench for the memory array. The method further includes recessing the metal within the deep trench for the memory array and the isolation region. The metal in the deep trench of the memory array is recessed to a greater depth than the metal in the isolation region.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: January 19, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Naoyoshi Kusaba, Oh-jung Kwon, Zhengwen Li, Hongwen Yan
  • Publication number: 20150364362
    Abstract: Embodiments of the present invention provide structures and methods for controlling stress in semiconductor wafers during fabrication. Features such as deep trenches (DTs) used in circuit elements such as trench capacitors impart stress on a wafer that is proportional to the surface area of the DTs. In embodiments, a corresponding pattern of dummy (non-functional) DTs is formed on the back side of the wafer to counteract the electrically functional DTs formed on the front side of a wafer. In some embodiments, the corresponding pattern on the back side is a mirror pattern that matches the functional (front side) pattern in size, placement, and number. By creating the minor pattern on both sides of the wafer, the stresses on the front and back of the wafer are in balance. This helps reduce topography issues such as warping that can cause problems during wafer fabrication.
    Type: Application
    Filed: June 17, 2014
    Publication date: December 17, 2015
    Inventors: Edward Engbrecht, Donghun Kang, Rishikesh Krishnan, Oh-jung Kwon, Karen A. Nummy
  • Patent number: 9087927
    Abstract: A trench structure that in one embodiment includes a trench present in a substrate, and a dielectric layer that is continuously present on the sidewalls and base of the trench. The dielectric layer has a dielectric constant that is greater than 30. The dielectric layer is composed of tetragonal phase hafnium oxide with silicon present in the grain boundaries of the tetragonal phase hafnium oxide in an amount ranging from 3 wt. % to 20 wt. %.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: July 21, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael P. Chudzik, Bachir Dirahoui, Rishikesh Krishnan, Siddarth A. Krishnan, Oh-jung Kwon, Paul C. Parries, Hongwen Yan
  • Patent number: 8963283
    Abstract: A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Oh-Jung Kwon, Junedong Lee, Paul C. Parries, Dominic J. Schepis