Abstract: A chip-lifetime testing instrument for semiconductor devices which can detect defective chips by testing the performance and electrical lifetime of the chips in manufacturing process of the semiconductor devices, so that the manufacturing cost can be reduced and unnecessary processes for packaging of defective chips can be avoided, thereby reducing the necessary space for the set-up of the testing instrument.

Abstract: A semi-conductor package having an insulator formed by a supporting portion, a mounting portion and connecting members, and a layer of electrically conductive material on the insulator in a pattern forming a pad and inner leads connected to the pad by supporting bars. A chip is attached on the pad, and the inner leads are wire-connected to the chip. The pad is vertically offset from the inner leads and the chip is supported in recessed fashion on the pad which shortens the length of the connecting wires whereby the wire-connecting efficiency and the structural stability are improved.