Abstract: A system-on-a-chip (SOC) includes a memory system, a data processor and a read only memory (ROM). The memory system includes random access memory and a memory controller. The data processor includes at least one functional block that communicates data with the memory system via the memory controller. The ROM stores data and one or more parity bits for detecting and correcting errors in the data. The data includes chip information and/or security information for the SOC. A method of using the SOC includes storing data in the ROM that includes chip information and/or security information for the SOC; storing in the ROM the one or more parity bits for the data; reading the data and the one or more parity bits from the ROM; detecting and correcting errors in the data using the one or more parity bits; and outputting the corrected data.

Abstract: A liquid crystal display device includes a liquid crystal display panel, a plurality of lamps for irradiating light onto the liquid crystal display panel, a cover bottom that houses the plurality of lamps, an inverter printed circuit board having a first surface and a second surface opposite to the first surface with an insulation base layer between the first and second surfaces, wherein the second surface is adjacent to the cover bottom, a transformer on the first surface of the inverter printed circuit board, and a metal shielding pattern on the second surface of the inverter printed circuit board directly between the transformer and the cover bottom.

Abstract: Provided are a composition for an oxide semiconductor thin film, a field effect transistor using the same and a method of fabricating the field effect transistor. The composition includes an aluminum oxide, a zinc oxide, an indium oxide and a tin oxide. The thin film formed of the composition is in amorphous phase. The field effect transistor having an active layer formed of the composition can have an improved electrical characteristic and be fabricated by a low temperature process.

Abstract: A backlight unit capable of preventing a degradation in luminance, while achieving a reduction in heat generation and a reduction in manufacturing costs by adjusting the arrangement of the light sources while reducing the number of the light sources is disclosed. The disclosed backlight unit includes a bottom cover formed with a plurality of light source groups each including a plurality of light sources arranged in one direction. The spacing of the adjacent light source groups increases gradually from a central portion of the bottom cover to opposite edges of the bottom cover.

Abstract: Disclosed is a printed circuit board, on which a holder for fixing a lamp is mounted, is disposed on an upper surface of a bottom cover, and an inverter supplying a driving voltage to the lamp is disposed on a lower surface of the bottom cover. The printed circuit board is electrically connected to the holder as a conductive pattern is embedded in the printed circuit board. The connector is directly mounted on the inverter, or it is connected to the inverter via a wire. In this case, the connector is also connected to the printed circuit board. Therefore, the connector of the inverter and the connector of the printed circuit board are electrically connected.

Abstract: Disclosed is a technique suitable for performing a stable protection function while satisfying a standard specification in the implementation of an LCC of a digital inverter for an LCD backlight. The LCC of a digital inverter for an LCD backlight comprises: a transformer which raises a AC power supplied from the inverter to an AC voltage of a high voltage for lighting a lamp; a voltage/current detection unit for detecting at least one of the current and voltage supplied to the lamp; an A/D converter for converting the detected voltage/current value of analog to a digital value; and an MCU which induces an LCC check point after the start of a striking process, compares at least one of the output current value and voltage value from the transformer with a preset reference value on the basis of an output signal of the A/D converter and then shuts down the inverter when the output current value or voltage value is determined to be abnormal.

Abstract: A liquid crystal display device includes a liquid crystal display panel, a plurality of lamps for irradiating light onto the liquid crystal display panel, a cover bottom that houses the plurality of lamps, an inverter printed circuit board having a first surface and a second surface opposite to the first surface with an insulation base layer between the first and second surfaces, wherein the second surface is adjacent to the cover bottom, a transformer on the first surface of the inverter printed circuit board, and a metal shielding pattern on the second surface of the inverter printed circuit board directly between the transformer and the cover bottom.

Abstract: A receiver performing a stable operation in a burst mode is provided. The receiver transmits packet data using a preamble, and has good acquisition performance so that a synchronization part converges on a preamble interval. For the acquisition performance, the receiver senses the carrier of a received signal, detects a rough location of a burst, and in response to the result of carrier sensing, performs coarse gain control, symbol timing compensation, and frame synchronization. Then, if the frame synchronization is completed, in response to the result of frame synchronization, the receiver performs fine gain control, equalization of the signal, and carrier recovery.

Abstract: A channel equalizing and carrier recovery system for home phoneline networking alliance (HomePNA) receiver and method thereof are provided. The channel equalizing system includes a frequency diverse quadrature amplitude modulation (FD-QAM) equalizer and a quadrature amplitude modulation (QAM) equalizer. The FD-QAM equalizer receives an FD-QAM signal, determines FD-QAM tap coefficients, and equalizes the FD-QAM signal using the FD-QAM tap coefficients. The QAM equalizer receives a QAM signal, determines QAM tap coefficients, and equalizes the QAM signal using the QAM tap coefficients. The QAM equalizer receives the FD-QAM signal and determines the QAM tap coefficients during a predetermined header period. The carrier recovery circuit includes a phase detector, a loop filter, and a numerically controlled oscillator (NCO).

Abstract: A digital echo cancellation device is provided. The digital echo cancellation device used for a high speed bidirectional communication system includes an adaptive beamformer in the form of a plurality of finite impulse response (FIR) filters for estimating an input receiving signal, the adaptive beamformer for estimating a front part, which rapidly changes in an echo path impulse response, by adaptively estimating the input receiving signal and an orthogonalized infinite impulse response (IIR) filter for receiving the estimated signal output from the adaptive beamformer and estimating a hind part of the echo path impulse response on the basis of an IIR. According to the digital echo cancellation device, the amount of calculation and the amount of required memory is significantly reduced, convergence speed is high, and the stability of the output of the filter is improved since the impulse response of the echo path is estimated by only several tens of taps.

Abstract: In a method for recognizing stations in a home network of an OFDM scheme and a method for establishing a link between stations in a home network having a plurality of stations, a node number is assigned to the each station and subchannels corresponding to each node number are assigned to each station, the starting station constructing tones corresponding to the subchannels assigned to its own node number and the node number of the destination station as single OFDM symbol, and placing the OFDM symbol in a frame for transmission, and stations other than the starting station detecting the tones from the frame, recovering the node number using indices of the subchannels obtained from the tones and recognizing the starting station and the destination station.

Abstract: A channel equalizing and carrier recovery system for home phoneline networking alliance (HomePNA) receiver and method thereof are provided. The channel equalizing system includes a frequency diverse quadrature amplitude modulation (FD-QAM) equalizer and a quadrature amplitude modulation (QAM) equalizer. The FD-QAM equalizer receives an FD-QAM signal, determines FD-QAM tap coefficients, and equalizes the FD-QAM signal using the FD-QAM tap coefficients. The QAM equalizer receives a QAM signal, determines QAM tap coefficients, and equalizes the QAM signal using the QAM tap coefficients. The QAM equalizer receives the FD-QAM signal and determines the QAM tap coefficients during a predetermined header period. The carrier recovery circuit includes a phase detector, a loop filter, and a numerically controlled oscillator (NCO).

Abstract: A receiver performing a stable operation in a burst mode is provided. The receiver transmits packet data using a preamble, and has good acquisition performance so that a synchronization part converges on a preamble interval. For the acquisition performance, the receiver senses the carrier of a received signal, detects a rough location of a burst, and in response to the result of carrier sensing, performs coarse gain control, symbol timing compensation, and frame synchronization. Then, if the frame synchronization is completed, in response to the result of frame synchronization, the receiver performs fine gain control, equalization of the signal, and carrier recovery.

Abstract: A pulse duration measuring apparatus generates a clock signal in the form of a clock pulse train having a period(T) and delays the clock signal and provides N-1 number of delayed clock signals, each of the delayed clock signals delayed by a delay time((T/N)*i), N being a positive integer and i being 1 to N-1 and counts the number of the clock pulses contained in the clock signal and each of the delayed clock signals, respectively, during the duration(Y) of the input pulse signal(I) and providing the count values. A pulse duration measuring apparatus detects a maximum counted value(n) among the counted values provided from the counting means and calculates the duration(Y) of the input pulse signal(I) based on the maximum count value(n).

Abstract: A method for decoding an encoded image signal supplied in the form of a series of encoded image frames, each of the encoded image frames being divided into a multiplicity of macroblocks of pixels, each of the macroblocks having an associated half-pixel resolution motion vector which represents a translatory motion of the macroblock between a present and its preceding frames of the encoded image signal to a half-pixel accuracy, comprises: providing differential pixels of a differential macroblock in a first predetermined scanning order by performing entropy decoding, inverse quantization and inverse transformation on the pixels in each macroblock of the present frame; scanning the differential pixels so as to provide scan converted differential pixels of a scan converted differential macroblock in a second predetermined scanning order; providing half-pixel resolution pixels of a half-pixel resolution macroblock in the second predetermined scanning order by accessing, under a control of the half-pixel resolutio

Abstract: An apparatus having a recording and reproducing unit for recording and reproducing an encoded video signal received from a transmitter comprises a first, a second and a third recording paths through which the encoded video signal is processed in a first recording mode, a second recording mode and a third recording mode in order to selectively record the processed video signal; and a fourth, a fifth and a sixth reproduction paths through which the video signal recorded in the first, the second or the third recording mode is retrieved by the recording and reproducing unit and processed for the displaying thereof.

Abstract: A memory apparatus for use in a receiver for decoding video signals comprises a first memory for storing an image frame; a second memory for storing current pixel data temporally and providing the same to said first memory; an address generator for generating address signals for sequentially addressing two-dimensional pixels in the blocks; a delay unit for delaying said address signals by a predetermined delay time in generating write address signals for said first memory; an offset unit for comparing the said address signals with an offset address so as to prohibit the provision of write address signals to said first memory until one of said address signals reaches to said offset address; and a control circuit for selectively providing the read address signals and the write address signals to said first memory.

Abstract: A high speed modular memory adapted for use in a decoding system of motion compensated prediction coded image data, comprises: 2.sup.N memory modules each comprising a two dimensional memory array with an address register for storing different pixels of a frame of the image data, wherein said N is a positive integer; a read/write signal generator for generating a read/write signal in response to a frame synchronization signal from the image data; an address generator for simultaneously generating a horizontal and a vertical addresses for each of the 2.sup.N memory modules in response to a motion vector separated into a horizontal motion vector and a vertical motion vector and the read/write control signal; a data bus for communicating the image data with the 2.sup.N memory modules; and an order changer which changes within the data bus positions of the data simultaneously read from the 2.sup.N memory modules within the data bus in response to the horizontal motion vector.

Abstract: An apparatus for recording and reproducing an encoded video signal from a source encoder comprises a decoder for performing a decoding process for the encoded video signal to produce a decoded video signal, an encoder block for compressing the decoded video signal using a spatial correlation to produce an intra mode compression signal, a buffer memory for storing the intra mode compression signal, a mode controller for generating a clock pulse used to read out data in the buffer memory in accordance with a longer playing time recording and a normal playing time recording and a recording and reproducing unit for recording and reproducing the intra mode compression signal read from the buffer memory.

Abstract: Disclosed herein is a memory system for storing a two dimensional digitized image signal consisting of a plurality of pixels arranged in (2.sup.M +X) columns and (2.sup.N +Y) rows, wherein X and Y do not exceed 2.sup.M-2 and 2.sup.N-1 respectively, and M and N are integers, comprising: a virtual address generator for generating (M+N+2) bits of a virtual address having (M+1) bits of a horizontal address component representing said (2.sup.M +X) columns and (N+1) bits of a vertical address component representing said (2.sup.N +Y) rows; a memory, having storage locations of 2.sup.M+N+1, for storing the two dimensional digitized image signal, each of the storage locations capable of storing one pixel data therein and addressable by (M+N+1 bits) of a physical address; and address mapping circuitry for changing the virtual address to the physical address.