Patents by Inventor Ohad Falik

Ohad Falik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220261357
    Abstract: Systems, apparatuses, and methods include technology that determines, with a neural network, that a first eviction node stored in a cache will be evicted from the cache based on a cache policy. The first eviction node is part of a plurality of nodes associated with a graph. Further, a subset of nodes of the plurality of nodes remains in the cache after the eviction of the first eviction node from the cache. The technology further tracks a number of cache hits on the cache during an aggregation operation associated with a hardware accelerator, where the aggregation operation is executed on the subset of nodes that remain in the cache after the eviction of the eviction node from the cache. The technology executes a training process on the neural network to adjust the cache policy based on the number of the cache hits.
    Type: Application
    Filed: May 2, 2022
    Publication date: August 18, 2022
    Inventors: Ronen Gabbai, Amit Bleiweiss, Ohad Falik, Amit Gur, Almog Tzabary
  • Publication number: 20220050791
    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.
    Type: Application
    Filed: July 26, 2021
    Publication date: February 17, 2022
    Inventors: Ben-Zion Friedman, Jacob Doweck, Eliezer Weissmann, James B. Crossland, Ohad Falik
  • Patent number: 11151074
    Abstract: Methods and apparatus to implement multiple inference compute engines are disclosed herein. A disclosed example apparatus includes a first inference compute engine, a second inference compute engine, and an accelerator on coherent fabric to couple the first inference compute engine and the second inference compute engine to a converged coherency fabric of a system-on-chip, the accelerator on coherent fabric to arbitrate requests from the first inference compute engine and the second inference compute engine to utilize a single in-die interconnect port.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: October 19, 2021
    Assignee: Intel Corporation
    Inventors: Israel Diamand, Roni Rosner, Ravi Venkatesan, Shlomi Shua, Oz Shitrit, Henrietta Bezbroz, Alexander Gendler, Ohad Falik, Zigi Walter, Michael Behar, Shlomi Alkalay
  • Patent number: 11074191
    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: July 27, 2021
    Assignee: Intel Corporation
    Inventors: Ben-Zion Friedman, Jacob Doweck, Eliezer Weissmann, James B. Crossland, Ohad Falik
  • Patent number: 10949736
    Abstract: Systems, apparatus and methods are described including operations for a flexible neural network accelerator.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: March 16, 2021
    Assignee: Intel Corporation
    Inventors: Michael E Deisher, Ohad Falik
  • Patent number: 10708328
    Abstract: Techniques to output a media stream, capture a media stream, or synchronize the output or capture of the media stream at a specified time are described. A media stream output or capture apparatus may include a media processor to receive a media stream to output or a request to capture a media stream and a start time. A buffer generator may be included to generate an input or an output buffer and a media mixer may be included to mix the media stream into the output buffer at the start time or capture the media stream from the input buffer at the start time.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Christopher Hall, Kevin B. Stanton, Pierre-Louis Bossart, Anthony S. Bock, Ohad Falik
  • Patent number: 10672401
    Abstract: Systems, apparatus and methods are described including operations for a dual mode GMM (Gaussian Mixture Model) scoring accelerator for both speech and video data.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: June 2, 2020
    Assignee: Intel Corporation
    Inventors: Nikhil Pantpratinidhi, Gokcen Cilingir, Michael Deisher, Ohad Falik, Michael Kounavis
  • Publication number: 20190370209
    Abstract: Methods and apparatus to implement multiple inference compute engines are disclosed herein. A disclosed example apparatus includes a first inference compute engine, a second inference compute engine, and an accelerator on coherent fabric to couple the first inference compute engine and the second inference compute engine to a converged coherency fabric of a system-on-chip, the accelerator on coherent fabric to arbitrate requests from the first inference compute engine and the second inference compute engine to utilize a single in-die interconnect port.
    Type: Application
    Filed: August 15, 2019
    Publication date: December 5, 2019
    Inventors: Israel Diamand, Roni Rosner, Ravi Venkatesan, Shlomi Shua, Oz Shitrit, Henrietta Bezbroz, Alexander Gendler, Ohad Falik, Zigi Walter, Michael Behar, Shlomi Alkalay
  • Patent number: 10488197
    Abstract: A device for positioning a tile, comprising: a beam reader for receiving a laser beam within a predetermined range of locations, and providing a height indication; a level for providing a tilt indication of a tilt of the device; a processor for receiving the height and tilt indications, and combining them for determining gradient and height of a part of the tile; a display component for displaying in at least two dimensions positioning information for the device, the positioning information relating to the gradient and height of the tile part, as obtained by combining the height and tilt indications, wherein the beam being received at a predetermined location within the range of locations, and the level indicating that the device is at a predetermined tilt, provides that the tile being positioned is at a required height, and wherein the device is adapted to be stably placed on the tile.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: November 26, 2019
    Assignee: CCT CREATIVE CONSTRUCTION TOOLS LTD.
    Inventors: Eyal Finkelstein, Ohad Falik
  • Patent number: 9973335
    Abstract: Examples are disclosed for exchanging a key between an input/output device for network device and a first processing element operating on the network device. Data having a destination associated with the first processing element may be received by the input/output device. The exchanged key may be used to encrypt the received data. The encrypted data may then be sent to a buffer maintained at least in part in a memory for the network device. The memory may be arranged to enable sharing of the buffer with at least a second processing element operating on the network device. Examples are also disclosed for the processing element to receive an indication of the storing of the encrypted data in the buffer. The processing element may then obtain the encrypted data from the buffer and decrypt the data using the exchanged key.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 15, 2018
    Assignee: INTEL CORPORATION
    Inventors: Ben-Zion Friedman, Eliezer Tamir, Eliel Louzoun, Ohad Falik
  • Publication number: 20180121796
    Abstract: Systems, apparatus and methods are described including operations for a flexible neural network accelerator.
    Type: Application
    Filed: November 3, 2016
    Publication date: May 3, 2018
    Inventors: Michael E DEISHER, Ohad FALIK
  • Publication number: 20180060246
    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.
    Type: Application
    Filed: November 3, 2017
    Publication date: March 1, 2018
    Applicant: Intel Corporation
    Inventors: Ben-Zion Friedman, Jacob Doweck, Eliezer Weissmann, James B. Crossland, Ohad Falik
  • Patent number: 9904346
    Abstract: Embodiments of an apparatus for improving performance for events handling are presented. In one embodiment, the apparatus includes a number of processing elements and task routing logic. If at least one of the processing elements is in a turbo mode, the task routing logic selects a processing element for executing a task based at least on a comparison of performance losses.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: February 27, 2018
    Assignee: Intel Corporation
    Inventors: Ryan D. Wells, Ohad Falik, Jose P. Allarey
  • Patent number: 9892069
    Abstract: Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic and posting logic. The look-up logic is to look-up an entry associated with an interrupt request to a virtual processor in a data structure. The posting logic is to post the interrupt request in a data structure specified by information in the first data structure.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: February 13, 2018
    Assignee: Intel Corporation
    Inventors: Rajesh Sankaran Madukkarumukumana, Gilbert Neiger, Ohad Falik, Sridhar Muthrasanallur, Gideon Gerzon
  • Publication number: 20180007373
    Abstract: Systems, apparatus and methods are described including operations for a dual mode GMM (Gaussian Mixture Model) scoring accelerator for both speech and video data.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 4, 2018
    Inventors: Nikhil PANTPRATINIDHI, Gokcen CILINGIR, Michael DEISHER, Ohad FALIK, Michael KOUNAVIS
  • Patent number: 9766683
    Abstract: A processor includes at least one core, a power control unit, and a first interconnect to couple with a peripheral controller. The first interconnect is to provide a first uni-directional communication path for communication of first power management data from the processor to the peripheral controller. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: September 19, 2017
    Assignee: Intel Corporation
    Inventors: Shaun M. Conrad, William Knolla, Douglas R. Moran, Sm M. Rahman, Jawad Haj-Yihia, Alon Naveh, Ohad Falik
  • Patent number: 9721569
    Abstract: Systems, apparatus and methods are described including operations for memory access via direct memory access engines, of a Gaussian Mixture Model Accelerator, corresponding to individual data streams.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: August 1, 2017
    Assignee: Intel Corporation
    Inventors: Ohad Falik, Michael E Deisher, Ioannis Yannis Schoinas, Jenny Chang, Hai Ming Khor
  • Publication number: 20170122735
    Abstract: A device for positioning a tile, comprising: a beam reader for receiving a laser beam within a predetermined range of locations, and providing a height indication; a level for providing a tilt indication of a tilt of the device; a processor for receiving the height and tilt indications, and combining them for determining gradient and height of a part of the tile; a display component for displaying in at least two dimensions positioning information for the device, the positioning information relating to the gradient and height of the tile part, as obtained by combining the height and tilt indications, wherein the beam being received at a predetermined location within the range of locations, and the level indicating that the device is at a predetermined tilt, provides that the tile being positioned is at a required height, and wherein the device is adapted to be stably placed on the tile.
    Type: Application
    Filed: June 15, 2015
    Publication date: May 4, 2017
    Inventors: Eyal FINKELSTEIN, Ohad FALIK
  • Patent number: 9612652
    Abstract: Methods and apparatus relating to controlling power consumption by a power management link are described. In one embodiment, the physical interface of a power management (PM) link is shut down when a processor is in a sleep state (e.g., to conserve power), while maintaining the availability of the processor for communication to a (e.g., embedded) controller over the PM link. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: September 29, 2012
    Date of Patent: April 4, 2017
    Assignee: Intel Corporation
    Inventors: Nir Rosenzweig, Efraim Rotem, Jawad Haj-Yihia, Ohad Falik
  • Patent number: 9571215
    Abstract: Methods and apparatus relating to measuring time offsets between devices with independent silicon clocks are described. In some embodiments, logic is provided to synchronize a first clock of a first agent with a second clock of a second agent based on one or more messages exchanged between the first agent and the second agent and a platform time. The first agent and the second agent are coupled via a link. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 14, 2017
    Assignee: Intel Corporation
    Inventors: Anthony S. Bock, Kevin B. Stanton, Ohad Falik, Mikal C. Hunsaker