Patents by Inventor Ohad Givaty

Ohad Givaty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10108514
    Abstract: A method for performing a regression session when testing a device under test (DUT), may include a. obtaining a coverage model of the DUT, and a verification session input file (VSIF) relating to a plurality of tests to be run on the DUT, the VSIF including an initial number of runs associated with each of the tests of the plurality of tests; b. performing a first iteration of the regression session in which each of the tests of the plurality of tests is run the initial number of runs associated with that test; c. calculating for that iteration an effectiveness grade of each run of the tests of the plurality of tests, and assigning a weight to each of the runs of the tests of the plurality of tests corresponding to the calculated effectiveness grade of that test run; an d.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: October 23, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yael Kinderman, Ohad Givaty
  • Patent number: 9838660
    Abstract: At least one example embodiment provides an apparatus including a processor configured to execute computer-readable instructions to receive image data from a plurality of pixels, determine a first white point based on the image data and a threshold percentage of a histogram of the image data, determine a second white point based on the image data, determine a third white point based on groups of the image data corresponding to a same hue or desaturation, the processor configured to divide the image data into the groups and determine an image based on at least the first white point, the second white point and the third white point.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: December 5, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Michael Dinerstein, Ohad Givaty
  • Patent number: 9208271
    Abstract: Embodiments provide methods, systems, and devices involving transaction correlation tools that may record a limited number of run attributes yet are likely to be important in the debugging process. Some embodiments may include novel tabular representations of the runs. Embodiments may allow the user to specify directives for the recording of the runs and the creation of these tables. Embodiments may include comparing sets of failing and passing runs, which may be generated at random. This approach is called statistical debugging, as it employs statistical tools to find attributes of the DVE that tend to co-occur with the failure.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: December 8, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Reshef Meir, Yael Kinderman, Yoav Hollander, Ohad Givaty
  • Patent number: 8903823
    Abstract: Embodiments provide tools and techniques for clustering failing runs in a design verification environment to aid in determining causes of the failing runs. Embodiments may include determining multiple failing runs of the design verification environment. Multiple partitions of the multiple failing runs may be generated. Each respective partition may partition one or more subsets of the multiple failing runs into one or more non-overlapping clusters of failing runs. The multiple partitions of the subsets of multiple failing runs may be merged into a hierarchical structure that includes at least one of the clusters. One or more clusters of failing runs from the merged hierarchical structure may be selected; these may be referred to as core clusters. Core clusters may be presented to a user based on the size and distance between the clusters.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: December 2, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Reshef Meir, Ohad Givaty, Yael Kinderman