Abstract: A semiconductor memory device in which performance is improved by reducing a wiring resistance is provided. The semiconductor memory device comprising an inter-wiring insulation film on a substrate, a first wiring pattern extending in a first direction, in the inter-wiring insulation film, a barrier insulation film that is on an upper surface of the inter-wiring insulation film, a barrier conductive pattern electrically connected to the first wiring pattern, in the barrier insulation film, a memory cell electrically connected to the barrier conductive pattern and including a selection pattern and a variable resistor pattern, and a second wiring pattern extending in a second direction intersecting the first direction, on the memory cell, wherein a width of the barrier conductive pattern in the second direction is different from a width in the second direction of a portion of the memory cell that is adjacent to the barrier conductive pattern.

Abstract: A method of manufacturing an MRAM device including forming a first insulating interlayer and a lower electrode contact, the lower electrode contact extending through the first insulating interlayer; forming a lower electrode layer, a magnetic tunnel junction layer, an upper electrode layer, and a first hard mask layer on the first insulating interlayer and lower electrode contact; forming a second hard mask on the first hard mask layer; etching the first hard mask layer and upper electrode layer to form a first hard mask and upper electrode; forming a spacer on sidewalls of the upper electrode and hard masks; and etching the magnetic tunnel junction layer and the lower electrode layer to form a structure including a lower electrode and a magnetic tunnel junction pattern on the lower electrode contact, wherein a layer remains on the upper electrode after etching the magnetic tunnel junction layer and the lower electrode layer.

Abstract: A memory device includes gate electrode layers stacked on top of each other on a substrate, a channel region on a cell region of the substrate and extending through the gate electrode layers in a direction perpendicular to an upper surface of the substrate, cell contacts connected to the gate electrode layers, an active region on a peripheral circuit region of the substrate, planar gate electrode layers on the peripheral circuit region and adjacent to the active region, a cover layer on the active region, and peripheral contacts connected to the active region and the planar gate electrode layers. At least a portion of the peripheral contacts are separated from the cover layer above the planar gate electrode layers.

Abstract: A method of manufacturing an MRAM device including forming a first insulating interlayer and a lower electrode contact, the lower electrode contact extending through the first insulating interlayer; forming a lower electrode layer, a magnetic tunnel junction layer, an upper electrode layer, and a first hard mask layer on the first insulating interlayer and lower electrode contact; forming a second hard mask on the first hard mask layer; etching the first hard mask layer and upper electrode layer to form a first hard mask and upper electrode; forming a spacer on sidewalls of the upper electrode and hard masks; and etching the magnetic tunnel junction layer and the lower electrode layer to form a structure including a lower electrode and a magnetic tunnel junction pattern on the lower electrode contact, wherein a layer remains on the upper electrode after etching the magnetic tunnel junction layer and the lower electrode layer.

Abstract: A memory device includes a plurality of gate electrode layers, an interlayer insulating layer, a plurality of contact plugs, and at least one contact insulating layer. The gate electrode layers extend in a first direction and have different lengths to form a step structure. The interlayer insulating layer is on the gate electrode layers. The contact plugs are connected to the gate electrode layers through the interlayer insulating layer. The at least one contact insulating layer is within the interlayer insulating layer and surrounds one or more of the contact plugs. The at least one contact insulating layer extends in the first direction.

Abstract: A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns.

Abstract: A memory device includes gate electrode layers stacked on top of each other on a substrate, a channel region on a cell region of the substrate and extending through the gate electrode layers in a direction perpendicular to an upper surface of the substrate, cell contacts connected to the gate electrode layers, an active region on a peripheral circuit region of the substrate, planar gate electrode layers on the peripheral circuit region and adjacent to the active region, a cover layer on the active region, and peripheral contacts connected to the active region and the planar gate electrode layers. At least a portion of the peripheral contacts are separated from the cover layer above the planar gate electrode layers.

Abstract: A memory device includes a plurality of gate electrode layers, an interlayer insulating layer, a plurality of contact plugs, and at least one contact insulating layer. The gate electrode layers extend in a first direction and have different lengths to form a step structure. The interlayer insulating layer is on the gate electrode layers. The contact plugs are connected to the gate electrode layers through the interlayer insulating layer. The at least one contact insulating layer is within the interlayer insulating layer and surrounds one or more of the contact plugs. The at least one contact insulating layer extends in the first direction.

Abstract: A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns.

Abstract: A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns.

Abstract: Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure.

Abstract: Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure.

Abstract: Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure.

Abstract: A semiconductor device and a method of forming patterns on a semiconductor device are disclosed. The semiconductor device may include high-density patterns with a minimum size that may be less the resolution limit of a photolithography process, and may have a substrate including a memory cell region and an adjacent connection region, a plurality of first conductive lines extending from the memory cell region to the connection region in a first direction, a plurality of second conductive lines connected from respective first conductive lines to a plurality of pads having a width equal to twice the width of each of the first conductive lines. The method may include two levels of spacer formation to provide sub resolution line widths and spaces as well as selected multiples of the minimum line widths and spaces.

Abstract: A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns.

Abstract: A semiconductor device and a method of forming patterns on a semiconductor device are disclosed. The semiconductor device may include high-density patterns with a minimum size that may be less the resolution limit of a photolithography process, and may have a substrate including a memory cell region and an adjacent connection region, a plurality of first conductive lines extending from the memory cell region to the connection region in a first direction, a plurality of second conductive lines connected from respective first conductive lines to a plurality of pads having a width equal to twice the width of each of the first conductive lines. The method may include two levels of spacer formation to provide sub resolution line widths and spaces as well as selected multiples of the minimum line widths and spaces.

Abstract: Methods of forming a semiconductor device can be provided by simultaneously forming a plurality of mask patterns using self-aligned reverse patterning, including respective mask pattern elements having different widths.

Abstract: Methods of forming a semiconductor device can be provided by simultaneously forming a plurality of mask patterns using self-aligned reverse patterning, including respective mask pattern elements having different widths.

Abstract: A method of forming a contact for a semiconductor device by forming a storage node contact in a semiconductor substrate having a first pad and a second pad formed thereon. The storage node contact is connected to the second pad. A bit line electrically insulated from the storage node contact by a spacer and electrically connected to the first pad.

Abstract: A method of forming a contact for a semiconductor device by forming a storage node contact in a semiconductor substrate having a first pad and a second pad formed thereon. The storage node contact is connected to the second pad. A bit line electrically insulated from the storage node contact by a spacer and electrically connected to the first pad.