Abstract: A method of manufacturing an MRAM device including forming a first insulating interlayer and a lower electrode contact, the lower electrode contact extending through the first insulating interlayer; forming a lower electrode layer, a magnetic tunnel junction layer, an upper electrode layer, and a first hard mask layer on the first insulating interlayer and lower electrode contact; forming a second hard mask on the first hard mask layer; etching the first hard mask layer and upper electrode layer to form a first hard mask and upper electrode; forming a spacer on sidewalls of the upper electrode and hard masks; and etching the magnetic tunnel junction layer and the lower electrode layer to form a structure including a lower electrode and a magnetic tunnel junction pattern on the lower electrode contact, wherein a layer remains on the upper electrode after etching the magnetic tunnel junction layer and the lower electrode layer.

Abstract: A method of manufacturing an MRAM device including forming a first insulating interlayer and a lower electrode contact, the lower electrode contact extending through the first insulating interlayer; forming a lower electrode layer, a magnetic tunnel junction layer, an upper electrode layer, and a first hard mask layer on the first insulating interlayer and lower electrode contact; forming a second hard mask on the first hard mask layer; etching the first hard mask layer and upper electrode layer to form a first hard mask and upper electrode; forming a spacer on sidewalls of the upper electrode and hard masks; and etching the magnetic tunnel junction layer and the lower electrode layer to form a structure including a lower electrode and a magnetic tunnel junction pattern on the lower electrode contact, wherein a layer remains on the upper electrode after etching the magnetic tunnel junction layer and the lower electrode layer.

Abstract: Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure.

Abstract: Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure.

Abstract: Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure.

Abstract: A semiconductor device and a method of forming patterns on a semiconductor device are disclosed. The semiconductor device may include high-density patterns with a minimum size that may be less the resolution limit of a photolithography process, and may have a substrate including a memory cell region and an adjacent connection region, a plurality of first conductive lines extending from the memory cell region to the connection region in a first direction, a plurality of second conductive lines connected from respective first conductive lines to a plurality of pads having a width equal to twice the width of each of the first conductive lines. The method may include two levels of spacer formation to provide sub resolution line widths and spaces as well as selected multiples of the minimum line widths and spaces.

Abstract: A semiconductor device and a method of forming patterns on a semiconductor device are disclosed. The semiconductor device may include high-density patterns with a minimum size that may be less the resolution limit of a photolithography process, and may have a substrate including a memory cell region and an adjacent connection region, a plurality of first conductive lines extending from the memory cell region to the connection region in a first direction, a plurality of second conductive lines connected from respective first conductive lines to a plurality of pads having a width equal to twice the width of each of the first conductive lines. The method may include two levels of spacer formation to provide sub resolution line widths and spaces as well as selected multiples of the minimum line widths and spaces.

Abstract: Methods of forming a semiconductor device can be provided by simultaneously forming a plurality of mask patterns using self-aligned reverse patterning, including respective mask pattern elements having different widths.

Abstract: Methods of forming a semiconductor device can be provided by simultaneously forming a plurality of mask patterns using self-aligned reverse patterning, including respective mask pattern elements having different widths.

Abstract: A method of forming a contact for a semiconductor device by forming a storage node contact in a semiconductor substrate having a first pad and a second pad formed thereon. The storage node contact is connected to the second pad. A bit line electrically insulated from the storage node contact by a spacer and electrically connected to the first pad.

Abstract: A method of forming a contact for a semiconductor device by forming a storage node contact in a semiconductor substrate having a first pad and a second pad formed thereon. The storage node contact is connected to the second pad. A bit line electrically insulated from the storage node contact by a spacer and electrically connected to the first pad.

Abstract: A shower head for adjusting distribution of a reactant gas in a process region of a semiconductor manufacturing reaction chamber, wherein a top plate has a gas port for introducing the reactant gas into the reaction chamber; a face plate, having through holes, disposed opposite the process region; a first baffle plate, having through holes, disposed between the top plate and the face plate and capable of moving up or down, wherein the first baffle plate has a top surface that defines a first gap for forming a first lateral flow passage; a second baffle plate, having through holes, disposed between the first baffle plate and the face plate and capable of moving up or down, wherein the second baffle plate has a top surface that defines a second gap for forming a second lateral flow passage; and a gap controller for determining widths of the first and second gaps.

Abstract: A shower head for adjusting distribution of a reactant gas in a process region of a semiconductor manufacturing reaction chamber, wherein a top plate has a gas port for introducing the reactant gas into the reaction chamber; a face plate, having through holes, disposed opposite the process region; a first baffle plate, having through holes, disposed between the top plate and the face plate and capable of moving up or down, wherein the first baffle plate has a top surface that defines a first gap for forming a first lateral flow passage; a second baffle plate, having through holes, disposed between the first baffle plate and the face plate and capable of moving up or down, wherein the second baffle plate has a top surface that defines a second gap for forming a second lateral flow passage; and a gap controller for determining widths of the first and second gaps.

Abstract: A shower head for adjusting distribution of a reactant gas in a process region of a semiconductor manufacturing reaction chamber, wherein a top plate has a gas port for introducing the reactant gas into the reaction chamber; a face plate, having through holes, disposed opposite the process region; a first baffle plate, having through holes, disposed between the top plate and the face plate and capable of moving up or down, wherein the first baffle plate has a top surface that defines a first gap for forming a first lateral flow passage; a second baffle plate, having through holes, disposed between the first baffle plate and the face plate and capable of moving up or down, wherein the second baffle plate has a top surface that defines a second gap for forming a second lateral flow passage; and a gap controller for determining widths of the first and second gaps.

Abstract: Provided is a method for fabricating a stacked capacitor with improved vertical and bottom etching profiles without electrical bridge between adjacent lower electrodes. Conductive layer for a lower electrode is deposited over an insulating layer whose top portion is made of a nitride etching barrier layer. During the etching of the conductive layer and subsequent overetching for lower electrode pattern, the nitride etching barrier layer serves an etching stopper and allows easier formation of polymer buildups on sidewalls of the lower electrode, more particularly on a bottom edge thereof. Resulting polymer buildups serve to prevent unacceptable bottom and sidewall etching of the lower electrode.