Patents by Inventor Oki Minabe

Oki Minabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7865345
    Abstract: Transaction-level simulation in which communication over a bus is performed by using a transaction. The transaction includes information indicating whether information is attribute information that is mapped to hardware and includes attribute information that is not mapped to hardware. The transaction is received, time information which is attribute that is not mapped to hardware is read from the transaction, and the result of the simulation based on the read time information is outputted.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: January 4, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masayuki Odagawa, Oki Minabe
  • Patent number: 7356717
    Abstract: A power saving type information processing apparatus is provided which is not expensive and can provide a high interruption performance without using an expensive and dedicated memory and a complicated software process. After an SDRAM setting register of an SDRAM controller outputs a SELF allowance signal for allowing SDRAM to transfer to a power saving mode from a normal operation mode, a WAITI command fetch detecting circuit outputs a WAITI command detecting signal. In this case, SDRAM is made to transfer to the power saving mode. If a CPU detects an external interruption while SDRAM is in the power saving mode, SDRAM is returned to the normal operation mode irrespective of settings of the SDRAM setting register.
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: April 8, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shinji Shiraga, Oki Minabe
  • Publication number: 20070006002
    Abstract: A power saving type information processing apparatus is provided which is not expensive and can provide a high interruption performance without using an expensive and dedicated memory and a complicated software process. After an SDRAM setting register of an SDRAM controller outputs a SELF allowance signal for allowing SDRAM to transfer to a power saving mode from a normal operation mode, a WAITI command fetch detecting circuit outputs a WAITI command detecting signal. In this case, SDRAM is made to transfer to the power saving mode. If a CPU detects an external interruption while SDRAM is in the power saving mode, SDRAM is returned to the normal operation mode irrespective of settings of the SDRAM setting register.
    Type: Application
    Filed: September 5, 2006
    Publication date: January 4, 2007
    Inventors: Shinji Shiraga, Oki Minabe
  • Publication number: 20060052995
    Abstract: Transaction-level simulation in which communication over a bus is performed by using a transaction. The transaction includes information indicating whether information is attribute information that is mapped to hardware and includes attribute information that is not mapped to hardware. The transaction is received, time information which is attribute that is not mapped to hardware is read from the transaction, and the result of the simulation based on the read time information is outputted.
    Type: Application
    Filed: September 8, 2005
    Publication date: March 9, 2006
    Applicant: Canon Kabushiki Kaisha
    Inventors: Masayuki Odagawa, Oki Minabe
  • Publication number: 20020026601
    Abstract: A power saving type information processing apparatus is provided which is not expensive and can provide a high interruption performance without using an expensive and dedicated memory and a complicated software process. After an SDRAM setting register of an SDRAM controller outputs a SELF allowance signal for allowing SDRAM to transfer to a power saving mode from a normal operation mode, a WAITI command fetch detecting circuit outputs a WAITI command detecting signal. In this case, SDRAM is made to transfer to the power saving mode. If a CPU detects an external interruption while SDRAM is in the power saving mode, SDRAM is returned to the normal operation mode irrespective of settings of the SDRAM setting register.
    Type: Application
    Filed: August 20, 2001
    Publication date: February 28, 2002
    Inventors: Shinji Shiraga, Oki Minabe