Patents by Inventor Olaf Grajetzky

Olaf Grajetzky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11403077
    Abstract: A method for preparing block diagrams having one or more blocks for code generation in a computing environment comprising a model editor, a data definition tool and a code generator. The block diagram is opened in the model editor, wherein a first block is a hierarchical block comprising a plurality of subordinate blocks, at least one input port and at least one output port connected by signals. Minimum values and maximum values are received for the input and output ports, determining scaling parameters for the input and output ports based on the received minimum and maximum values. Scaling parameters are determined for each subordinate block in the first block, wherein the scaling parameters of at least one subordinate block are determined based on the scaling parameters of at least one output port. Also, a method for generating program code, a non-transitory computer readable medium and a computer system are provided.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: August 2, 2022
    Assignee: dSPACE GmbH
    Inventors: Johannes Scherle, Anders Johansson, Olaf Grajetzky
  • Publication number: 20210034337
    Abstract: A method for preparing block diagrams having one or more blocks for code generation in a computing environment comprising a model editor, a data definition tool and a code generator. The block diagram is opened in the model editor, wherein a first block is a hierarchical block comprising a plurality of subordinate blocks, at least one input port and at least one output port connected by signals. Minimum values and maximum values are received for the input and output ports, determining scaling parameters for the input and output ports based on the received minimum and maximum values. Scaling parameters are determined for each subordinate block in the first block, wherein the scaling parameters of at least one subordinate block are determined based on the scaling parameters of at least one output port. Also, a method for generating program code, a non-transitory computer readable medium and a computer system are provided.
    Type: Application
    Filed: August 3, 2020
    Publication date: February 4, 2021
    Applicant: dSPACE digital signal processing and control engineering GmbH
    Inventors: Johannes SCHERLE, Anders JOHANSSON, Olaf GRAJETZKY
  • Patent number: 9977417
    Abstract: A method and a system for optimizing utilization of a programmable logic element for use in an electronic control unit for vehicles, wherein the programmable logic element has a soft CPU and/or an unused remaining area. A plurality of model variants is generated that reproduce functionality of the control unit, and generate a plurality of soft CPU configurations with differing configuration scope, which occupy an area corresponding to the configuration scope of the programmable logic element, and execute processor-in-the-loop simulations for the plurality of model variants and/or soft CPU configurations after instantiation of the soft CPU corresponding to the soft CPU configuration on a programmable logic element. The profiling data acquired for the soft CPU during the PIL simulation is used with regard to the processing of the input signal for optimizing utilization of the programmable logic element.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: May 22, 2018
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventor: Olaf Grajetzky
  • Publication number: 20150205281
    Abstract: A method and a system for optimizing utilization of a programmable logic element for use in an electronic control unit for vehicles, wherein the programmable logic element has a soft CPU and/or an unused remaining area. A plurality of model variants is generated that reproduce functionality of the control unit, and generate a plurality of soft CPU configurations with differing configuration scope, which occupy an area corresponding to the configuration scope of the programmable logic element, and execute processor-in-the-loop simulations for the plurality of model variants and/or soft CPU configurations after instantiation of the soft CPU corresponding to the soft CPU configuration on a programmable logic element. The profiling data acquired for the soft CPU during the PIL simulation is used with regard to the processing of the input signal for optimizing utilization of the programmable logic element.
    Type: Application
    Filed: January 22, 2015
    Publication date: July 23, 2015
    Applicant: dSPACE digital signal processing and control engineering GmbH
    Inventor: Olaf Grajetzky