Patents by Inventor Olaf Luthje

Olaf Luthje has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dynamic host code generation from architecture description for fast simulation
    Patent number: 9830174
    Abstract: Systems and methods of dynamic host code generation from architecture description for fast simulation. In accordance with a method embodiment of the present invention, a method of simulating execution of a first plurality of processor instructions written in a first instruction set comprises generating a second plurality of processor instructions in a second instruction set for emulating the first plurality of processor instructions. The generating is based upon the high level description of the instruction set and/or simulated state information during the simulating.
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: November 28, 2017
    Assignee: Synopsys, Inc.
    Inventors: Jacques Van Damme, Achim Nohl, Olaf Luthje
  • User interface for facilitation of high level generation of processor extensions
    Patent number: 9064076
    Abstract: Systems and methods of user interface for facilitation of high level generation of processor extensions. In accordance with a method embodiment of the present invention, an instruction format is accessed at a graphical user interface. A programming language description of a computation element for an execution unit of the processor extension is accessed. A representation of a hardware design for the processor extension comprising the instruction format and the computation element is generated.
    Type: Grant
    Filed: March 23, 2006
    Date of Patent: June 23, 2015
    Assignees: Synopsys, Inc., MIPS Technologies, Inc.
    Inventors: Gunnar Braun, Frank Fiedler, Andreas Hoffmann, Gideon Intrater, Olaf Lüthje, Achim Nohl, Ludwig Rieder
  • Dynamic host code generation from architecture description for fast simulation
    Publication number: 20070150873
    Abstract: Systems and methods of dynamic host code generation from architecture description for fast simulation. In accordance with a method embodiment of the present invention, a method of simulating execution of a first plurality of processor instructions written in a first instruction set comprises generating a second plurality of processor instructions in a second instruction set for emulating the first plurality of processor instructions. The generating is based upon the high level description of the instruction set and/or simulated state information during the simulating.
    Type: Application
    Filed: October 19, 2006
    Publication date: June 28, 2007
    Inventors: Jacques Van Damme, Achim Nohl, Olaf Luthje